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Merge pull request #167 from mithro/verilog-fix-3 

verilog: Fix ordering of ports on mux primitives.
This commit is contained in:
Tim Ansell 2020-10-06 08:29:53 -07:00 committed by GitHub
parent 3ac9f24a1b 795158aa4b
commit f3ed3d7154
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15 changed files with 15 additions and 15 deletions
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libraries/sky130_fd_sc_hdll/latest

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libraries/sky130_fd_sc_ls/v0.1.1

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libraries/sky130_fd_sc_ms/v0.0.1

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libraries/sky130_fd_sc_ms/v0.0.2

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