Merge a512ddf81a into 49d3c73c2c
This commit is contained in:
Grzegorz Latosiński
GitHub
commit
c78a53bd3d
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@ -17,9 +17,11 @@ name: skywater-pdk-scripts
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channels:
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- symbiflow
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- defaults
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- conda-forge
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dependencies:
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- python=3.8
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- pip
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- ngspice
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# Packages installed from PyPI
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- pip:
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- -r requirements.txt
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@ -4,5 +4,8 @@ flake8
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# previews.
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rst_include
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# the PySpice module for rendering FET bins plots
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PySpice
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# The Python API for the SkyWater PDK.
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-e scripts/python-skywater-pdk
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@ -22,12 +22,16 @@ import os
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from dataclasses import dataclass
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from dataclasses_json import dataclass_json
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from enum import Enum
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from typing import Optional, Union, Tuple
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from typing import Optional, Union, Tuple, List
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from collections import namedtuple
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from pathlib import Path
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import csv
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from .utils import comparable_to_none
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from .utils import dataclass_json_passthru_config as dj_pass_cfg
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FETBin = namedtuple('FETBin', ['device', 'bin', 'w', 'l'])
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LibraryOrCell = Union['Library', 'Cell']
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@ -545,6 +549,24 @@ class Cell:
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self))
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return "{}__{}".format(self.library.fullname, self.name)
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@classmethod
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def parse_bins(cls, binsfile) -> List[FETBin]:
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"""
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Parse bins.csv file.
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Parameters
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----------
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binsfile: path to the bins.csv file
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"""
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with open(binsfile, 'r') as f:
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reader = csv.reader(f)
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next(reader)
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res = []
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for line in reader:
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res.append(FETBin(line[0], int(line[1]), float(line[2]), float(line[3])))
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return res
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@classmethod
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def parse(cls, s):
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kw = {}
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@ -555,7 +577,6 @@ class Cell:
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return cls(**kw)
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if __name__ == "__main__":
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import doctest
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doctest.testmod()
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@ -0,0 +1,300 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright 2020 SkyWater PDK Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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"""Module for creating FET characteristics plots from bins.csv files.
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This module allows simulating FET cells and creating:
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* Id/W vs gm/Id
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* fT vs gm/Id
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* gm/gds vs gm/Id
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* gm/Id vs Vgg
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plots based on different FET length and width values from bins.csv file.
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"""
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import PySpice.Logging.Logging as Logging
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from PySpice.Spice.Netlist import Circuit
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from PySpice.Unit import u_V
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import matplotlib.pyplot as plt
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from pathlib import Path
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import csv
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from collections import defaultdict
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import os
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import sys
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sys.path.insert(0, os.path.abspath(__file__ + '/../../../../'))
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from skywater_pdk.base import Cell
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logger = Logging.setup_logging()
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def create_test_circuit(fet_type, fet_L, fet_W, corner_path):
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"""
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Creates a simple test circuit that contains only given FET.
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Parameters
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----------
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fet_type: name of the FET model
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fet_L: FET length
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fet_W: FET width
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corner_path:
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path to the spice corner file with model definitions and parameters
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"""
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c = Circuit('gm_id')
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c.include(corner_path)
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# create the circuit
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c.V('gg', 1, c.gnd, 0@u_V)
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c.V('dd', 2, c.gnd, 1.8@u_V)
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c.X(
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'M1', fet_type, 2, 1, c.gnd, c.gnd, L=fet_L, W=fet_W, ad="'W*0.29'",
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pd="'2*(W+0.29)'", as_="'W*0.29'", ps="'2*(W+0.29)'", nrd="'0.29/W'",
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nrs="'0.29/W'", sa=0, sb=0, sd=0, nf=1, mult=1
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)
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return c
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def run_sim(c, iparam, fet_W):
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"""
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Runs simulation for a given circuit with FET cell.
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Parameters
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----------
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c: circuit to simulate
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iparam:
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template string for creating internal parameter names (gm, id, gds,
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cgg) for a given FET
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fet_W: FET width
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"""
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sim = c.simulator()
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sim.save_internal_parameters(
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iparam % 'gm', iparam % 'id', iparam % 'gds', iparam % 'cgg'
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)
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try:
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# run the dc simulation
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an = sim.dc(Vgg=slice(0, 1.8, 0.01))
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# calculate needed values..need as_ndarray() since most of these have
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# None as the unit and that causes an error
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gm_id = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
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an.internal_parameters[iparam % 'id'].as_ndarray())
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ft = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
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an.internal_parameters[iparam % 'cgg'].as_ndarray())
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id_W = (an.internal_parameters[iparam % 'id'].as_ndarray() / fet_W)
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gm_gds = (an.internal_parameters[iparam % 'gm'].as_ndarray() /
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an.internal_parameters[iparam % 'gds'].as_ndarray())
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except Exception:
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sim.ngspice.destroy('all')
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sim.ngspice.reset()
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raise
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sim.ngspice.destroy('all')
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sim.ngspice.reset()
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return gm_id, ft, id_W, gm_gds, an.nodes['v-sweep']
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def init_plots(fet_name, W):
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"""
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Initializes plots for FET bins simulation.
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Parameters
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----------
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fet_name: name of the current FET cell
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W: FET width
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"""
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figs = [plt.figure(), plt.figure(), plt.figure(), plt.figure()]
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plots = [f.subplots() for f in figs]
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figs[0].suptitle(f'{fet_name} Id/W vs gm/Id (W = {W})')
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plots[0].set_xlabel("gm/Id")
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plots[0].set_ylabel("Id/W")
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plots[0].grid(True)
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figs[1].suptitle(f'{fet_name} fT vs gm/Id (W = {W})')
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plots[1].set_xlabel("gm/Id")
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plots[1].set_ylabel("f_T")
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plots[1].grid(True)
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figs[2].suptitle(f'{fet_name} gm/gds vs gm/Id (W = {W})')
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plots[2].set_xlabel("gm/Id")
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plots[2].set_ylabel("gm/gds")
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plots[2].grid(True)
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figs[3].suptitle(f'{fet_name} gm/Id vs Vgg (W = {W})')
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plots[3].set_xlabel("Vgg")
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plots[3].set_ylabel("gm/Id")
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plots[3].grid(True)
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return figs, plots
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def gen_plots(gm_id, id_W, ft, gm_gds, vsweep, fet_W, fet_L, plots):
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"""
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Generates plot lines for FET bins simulation parameters.
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Parameters
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----------
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gm_id: gm/Id values
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id_W: Id/W values
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ft: f_T values
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gm_gds: gm/gds values
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vsweep: v-sweep values
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fet_W: FET width
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fet_L: FET length
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plots: plots on which plot lines should be drawn
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"""
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# plot some interesting things
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plots[0].plot(gm_id, id_W, label=f'W {fet_W} x L {fet_L}')
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plots[1].plot(gm_id, ft, label=f'W {fet_W} x L {fet_L}')
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plots[2].plot(gm_id, gm_gds, label=f'W {fet_W} x L {fet_L}')
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plots[3].plot(vsweep, gm_id, label=f'W {fet_W} x L {fet_L}')
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def close_plots(figures):
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"""
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Closes plots.
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"""
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for figure in figures:
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plt.close(figure)
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def generate_fet_plots(
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corner_path,
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bins_csv,
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outdir,
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outprefix,
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only_W=None,
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ext='svg'):
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"""
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Generates FET bins plots.
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Parameters
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----------
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corner_path: Path to FET model definitions and parameters
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bins_csv: Path to the CSV file with bin parameters and FET model names
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outdir: Directory where outputs should be stored
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outprefix: Prefix for the output plot images
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only_W: List of FET widths for which the plots should be generated
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ext: extension for plot files
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"""
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print(f'[generate_fet_plots] {corner_path} {bins_csv}' +
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f'{outdir} {outprefix} {only_W}')
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bins = Cell.parse_bins(bins_csv)
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bins_by_W = defaultdict(list)
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# group bins by W
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for fetbin in bins:
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bins_by_W[(fetbin.device, fetbin.w)].append(fetbin)
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Ws = [key for key in bins_by_W.keys()
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if only_W is None or key[1] in only_W]
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for fet_type, W in Ws:
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if outprefix is None:
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outprefix = fet_type
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print(f'======> {fet_type}: {W}')
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iparam = f'@m.xm1.m{fet_type}[%s]'
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# fet_W and fet_L values here are only for initialization, they are
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# later changed in the for loop
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c = create_test_circuit(fet_type, 0.15, 1, corner_path)
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figures, plots = init_plots(fet_type, W)
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try:
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for fetbin in bins_by_W[(fet_type, W)]:
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if only_W is not None and fetbin.w not in only_W:
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continue
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c.element('XM1').parameters['W'] = fetbin.w
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c.element('XM1').parameters['L'] = fetbin.l
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gm_id, ft, id_W, gm_gds, vsweep = run_sim(c, iparam, fetbin.w)
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gen_plots(gm_id, id_W, ft, gm_gds, vsweep, fetbin.w, fetbin.l, plots)
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except Exception:
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close_plots(figures)
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raise
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figtitles = ['Id_w', 'fT', 'gm_gds', 'gm_id']
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for figure, name in zip(figures, figtitles):
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lg = figure.legend(
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bbox_to_anchor=(1.05, 1),
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loc='upper left'
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)
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figure.tight_layout()
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figure.savefig(
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Path(outdir) / (
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outprefix +
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f'_{fet_type}_{name}_W{str(W).replace(".", "_")}.{ext}'),
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bbox_extra_artists=(lg,),
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bbox_inches='tight'
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)
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close_plots(figures)
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def main(argv):
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import argparse
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parser = argparse.ArgumentParser(
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prog=argv[0],
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description=__doc__,
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formatter_class=argparse.RawDescriptionHelpFormatter
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)
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parser.add_argument(
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'corner_path',
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help='Path to corner SPICE file containing FET definition',
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type=Path
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)
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parser.add_argument(
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'bins_csv',
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help='Path to CSV file with fet_type, bin, fet_W and fet_L parameters',
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type=Path
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)
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parser.add_argument(
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'outdir',
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help='Path to the directory to save the plots to',
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type=Path
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)
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parser.add_argument(
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'--outprefix',
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help='The prefix to add to plot file names'
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)
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parser.add_argument(
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'--only-w',
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help='Simulate the FET only for a given fet_W values',
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nargs='+',
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type=float
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)
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parser.add_argument(
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'--ext',
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help='The image extension to use for figures',
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default='svg'
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)
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args = parser.parse_args(argv[1:])
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generate_fet_plots(
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args.corner_path,
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args.bins_csv,
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args.outdir,
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args.outprefix,
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args.only_w,
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args.ext)
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return 0
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if __name__ == '__main__':
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sys.exit(main(sys.argv))
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|
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@ -0,0 +1,131 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
|
||||
#
|
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# Copyright 2020 SkyWater PDK Authors
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# https://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
"""Creates plots for FET characteristics for FET cells in Skywater libraries.
|
||||
|
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This script scans for FET cells in the Skywater PDK libraries and generates
|
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the FET cells using methods from the fet submodule.
|
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"""
|
||||
|
||||
|
||||
import argparse
|
||||
from pathlib import Path
|
||||
import sys
|
||||
import contextlib
|
||||
import traceback
|
||||
import errno
|
||||
|
||||
from fet import generate_fet_plots
|
||||
|
||||
|
||||
def main(argv):
|
||||
parser = argparse.ArgumentParser(
|
||||
prog=argv[0],
|
||||
description=__doc__,
|
||||
formatter_class=argparse.RawDescriptionHelpFormatter
|
||||
)
|
||||
parser.add_argument(
|
||||
'libraries_dir',
|
||||
help='Path to the libraries directory of skywater-pdk',
|
||||
type=Path
|
||||
)
|
||||
parser.add_argument(
|
||||
'corner_file',
|
||||
help='Path to the corner SPICE file',
|
||||
type=Path
|
||||
)
|
||||
parser.add_argument(
|
||||
'output_dir',
|
||||
help='Path to the output directory',
|
||||
type=Path
|
||||
)
|
||||
parser.add_argument(
|
||||
'--libname',
|
||||
help='Library name to generate the Symbolator diagrams for',
|
||||
type=str
|
||||
)
|
||||
parser.add_argument(
|
||||
'--version',
|
||||
help='Version for which the Symbolator diagrams should be generated',
|
||||
type=str
|
||||
)
|
||||
parser.add_argument(
|
||||
'--create-dirs',
|
||||
help='Create directories for output when not present',
|
||||
action='store_true'
|
||||
)
|
||||
parser.add_argument(
|
||||
'--failed-inputs',
|
||||
help=('Path to an output file which will store all input filenames ' +
|
||||
'for which ngspice failed to simulate'
|
||||
),
|
||||
type=Path
|
||||
)
|
||||
|
||||
args = parser.parse_args(argv[1:])
|
||||
|
||||
fetbins = list(args.libraries_dir.rglob('*fet*bins.csv'))
|
||||
|
||||
nc = contextlib.nullcontext()
|
||||
|
||||
with open(args.failed_inputs, 'w') if args.failed_inputs else nc as err:
|
||||
for fetbin in fetbins:
|
||||
outdir = (args.output_dir /
|
||||
fetbin.parent.resolve()
|
||||
.relative_to(args.libraries_dir.resolve()))
|
||||
library = outdir.relative_to(args.output_dir).parts[0]
|
||||
ver = outdir.relative_to(args.output_dir).parts[1]
|
||||
if args.libname and args.libname != library:
|
||||
continue
|
||||
if args.version and args.version != ver:
|
||||
continue
|
||||
print(f'===> {str(fetbin)}')
|
||||
try:
|
||||
if not outdir.exists():
|
||||
if args.create_dirs:
|
||||
outdir.mkdir(parents=True)
|
||||
else:
|
||||
print(f'The output directory {str(outdir)} is missing')
|
||||
print('Run the script with --create-dirs')
|
||||
return errno.ENOENT
|
||||
|
||||
prefix = fetbin.name.replace('.bins.csv', '')
|
||||
generate_fet_plots(
|
||||
args.corner_file,
|
||||
fetbin,
|
||||
outdir,
|
||||
f'{prefix}_',
|
||||
ext='sim.svg'
|
||||
)
|
||||
except (Exception, IndexError):
|
||||
print(
|
||||
f'Failed to generate FET plot for {str(fetbin)}',
|
||||
file=sys.stderr
|
||||
)
|
||||
traceback.print_exc()
|
||||
if err:
|
||||
err.write(f'{fetbin}\n')
|
||||
|
||||
print('Finished generating FET plots')
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
sys.exit(main(sys.argv))
|
||||
Loading…
Reference in New Issue