docs: Renaming so docs match `sky130_fd_pr` cell names.

* Make the directory names consistent with cell names.
 * Add `:model:` and `:cell:` around object names.
 * Small other cleanups.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

docs/rules/device-details/bipolar-npn/index.rst

@@ -1,51 +0,0 @@
-Bipolar (NPN)
--------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__npn4`
--  Model Names: :model:`sky130_fd_pr_base__npnpar1x1`, :model:`sky130_fd_pr_base__npnpar1x2`, :model:`sky130_fd_pr_base__npn_1x1_2p0_hv`
-
-Operating regime where SPICE models are valid
-
--  \|V\ :sub:`CE`\ \| = 0 to 5.0V
--  \|V\ :sub:`BE`\ \| = 0 to 5.0V
--  I\ :sub:`CE` = 0.01 to 10 µA/µm\ :sup:`2`
-
-Details
-~~~~~~~
-
-The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available:
-
--  ungated device with emitter 1.0 x 1.0
--  ungated device with emitter 1.0 x 2.0
--  poly-gated version with octagonal emitter of A = 1.97 µm\ :sup:`2`
-
-The :model:`sky130_fd_pr_base__npn_1x1_2p0_hv` device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal.
-
-Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below:
-
-
-.. include:: bipolar-npn-table0.rst
-
-
-
-Symbols for the npnpar are shown below
-
-|symbol-bipolar-npn-1| |symbol-bipolar-npn-2| |symbol-bipolar-npn-3|
-
-The cross-section of the :model:`sky130_fd_pr_base__npnpar1x1`/:model:`sky130_fd_pr_base__npnpar1x2` is shown below.
-
-|cross-section-bipolar-npnpar1x|
-
-The cross-section of the :model:`sky130_fd_pr_base__npn_1x1_2p0_hv` is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on.
-
-|cross-section-bipolar-npn_1x1_2p0_hv|
-
-.. |symbol-bipolar-npn-1| image:: symbol-bipolar-npn-1.svg
-.. |symbol-bipolar-npn-2| image:: symbol-bipolar-npn-2.svg
-.. |symbol-bipolar-npn-3| image:: symbol-bipolar-npn-3.svg
-.. |cross-section-bipolar-npnpar1x| image:: cross-section-bipolar-npnpar1x.svg
-.. |cross-section-bipolar-npn_1x1_2p0_hv| image:: cross-section-bipolar-npn_1x1_2p0_hv.svg
-

docs/rules/device-details/cap_mim/index.rst

@@ -4,8 +4,8 @@ MiM Capacitor
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__mimcap34`, :cell:`sky130_fd_pr_base__mimcap45`
--  Model Names: :model:`sky130_fd_pr_base__xcmimc`, :model:`sky130_fd_pr_base__xcmim2c`
+-  Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base`
+-  Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4`
 
 Operating Voltages where SPICE models are valid
 
@@ -24,13 +24,13 @@ The constructions are identical, and the capacitors may be stacked to maximize t
 Electrical specs are listed below:
 
 
-.. include:: capacitors-mim-table0.rst
+.. include:: cap_mim-table0.rst
 
 
 
 The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate.
 
-|symbol-capacitor-mim|
+|symbol-cap_mim|
 
 Cell name
 
@@ -40,8 +40,8 @@ Calc capacitance
 
 The cross-section of the “stacked” MiM capacitor is shown below:
 
-|cross-section-capacitor-mim|
+|cross-section-cap_mim|
 
-.. |symbol-capacitor-mim| image:: symbol-capacitor-mim.svg
-.. |cross-section-capacitor-mim| image:: cross-section-capacitor-mim.svg
+.. |symbol-cap_mim| image:: symbol-cap_mim.svg
+.. |cross-section-cap_mim| image:: cross-section-cap_mim.svg
 

docs/rules/device-details/cap_var/index.rst

@@ -4,8 +4,8 @@ Varactors
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__capbn_b`
--  Model Name: :model:`sky130_fd_pr_base__xcnwvc`, :model:`sky130_fd_pr_base__xcnwvc2`
+-  Cell Name: :cell:`capbn_b`
+-  Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt`
 -  Model Type: subcircuit
 
 Operating Voltages where SPICE models are valid
@@ -17,13 +17,13 @@ Details
 
 The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model:
 
--  xcnwvc—low VT PMOS device option
--  xcnwvc2—high VT PMOS device option
+-  :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option
+-  :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option
 
 The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request.
 
 
-.. include:: varactors-table0.rst
+.. include:: cap_var-table0.rst
 
 
 
@@ -31,13 +31,13 @@ There is no equivalent varactor for 5V operation. The NHV or PHV devices should
 
 The symbols for the varactors are shown below:
 
-|symbol-varactors-a| |symbol-varactors-b|
+|symbol-cap_var-a| |symbol-cap_var-b|
 
 The cross-section of the varactor is shown below:
 
-|cross-section-varactors|
+|cross-section-cap_var|
 
-.. |symbol-varactors-a| image:: symbol-varactors-a.svg
-.. |symbol-varactors-b| image:: symbol-varactors-b.svg
-.. |cross-section-varactors| image:: cross-section-varactors.svg
+.. |symbol-cap_var-a| image:: symbol-cap_var-a.svg
+.. |symbol-cap_var-b| image:: symbol-cap_var-b.svg
+.. |cross-section-cap_var| image:: cross-section-cap_var.svg
 

docs/rules/device-details/cap_vpp/cap_vpp-table0.rst

@@ -15,77 +15,77 @@
      - 310.8
      - 386
      - fF/cell
-     - xcmvppx4\_2xnhvnative10x4, in inversion
+     - :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5_nhv`, in inversion
 
    * - VPP100LISM1M2M3
      - 96.99
      - 82.92
      - 111.05
      - fF/cell
-     - xcmvpp11p5x11p7\_m3\_lishield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1`
 
    * - VPP100M1M2
      - 74.6
      - 57.82
      - 91.39
      - fF/cell
-     - xcmvpp11p5x11p7\_m1m2
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield`
 
    * - VPP100M1M4M5S
      - 108.4
      - 92.79
      - 124
      - fF/cell
-     - xcmvpp11p5x11p7\_m1m4m5shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldm5`
 
    * - VPP12LISM1M2M3
      - 10.69
      - 8.29
      - 13.1
      - fF/cell
-     - xcmvpp4p4x4p6\_m3\_lishield
+     - :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1`
 
    * - VPP12M1M2
      - 7.81
      - 6.05
      - 9.57
      - fF/cell
-     - xcmvpp4p4x4p6\_m1m2
+     - :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield`
 
    * - VPP1LIM1M2
      - 0.78
      - 0.62
      - 0.95
      - fF/cell
-     - xcmvpp1p8x1p8
+     - :model:`sky130_fd_pr__cap_vpp_01p8x01p8_m1m2_noshield`
 
    * - VPP25PYSM1M4M5S
      - 42.11
      - TBD
      - TBD
      - fF/cell
-     - xcmvpp6p8x6p1\_polym5shield
+     - :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3m4_shieldpo_floatm5`
 
    * - VPP50LISM123M5S
      - 42.75
      - 33.35
      - 50.87
      - fF/cell
-     - xcmvpp8p6x7p9\_m3\_lim5shield
+     - :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4`
 
    * - VPP50LISM1M2M3
      - TBD
      - 34.63
      - 50.87
      - fF/cell
-     - xcmvpp8p6x7p9\_m3\_lishield
+     - :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1`
 
    * - VPPSYM3
      - 35
      - 24.5
      - 45.5
      - fF/cell
-     - xcmvpp3
+     - :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield`
 
    * - VPPSYM4
      - 9.48
@@ -99,47 +99,47 @@
      - 3.06
      - 5.68
      - fF/cell
-     - xcmvpp5
+     - :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield`
 
    * - VPP\_100\_LIM5S
      - 116.75
      - 99.94
      - 133.56
      - fF/cell
-     - xcmvpp11p5x11p7\_lim5shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5`
 
    * - VPP\_100\_M3S
      - 97.56
      - 84.63
      - 110.79
      - fF/cell
-     - xcmvpp11p5x11p7\_m3shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2_shieldpom3`
 
    * - VPP\_100\_M4S
      - 118.5
      - 94.82
      - 142.2
      - fF/cell
-     - xcmvpp11p5x11p7\_m4shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4`
 
    * - VPP\_100\_M5S
      - 137.45
      - 117.66
      - 157.24
      - fF/cell
-     - xcmvpp11p5x11p7\_m5shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5`
 
    * - VPP\_100\_POLYM4S
      - 121.9
      - 97.51
      - 146.3
      - fF/cell
-     - xcmvpp11p5x11p7\_polym4shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldpom4`
 
    * - VPP\_100\_POLYM5S
      - 141.23
      - 120.89
      - 161.57
      - fF/cell
-     - xcmvpp11p5x11p7\_polym5shield
+     - :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5`
 

docs/rules/device-details/cap_vpp/index.rst

@@ -0,0 +1,93 @@
+Vertical Parallel Plate (VPP) capacitors
+----------------------------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))`
+-  Model Names: :model:`sky130_fd_pr__cap_vpp_*`
+
+   -  X and Y are size dimentions
+   -  MM refers to the layers which are used for the capacitance
+   -  SS refers to the layers which are used as shields (`noshield` when no shield is used)
+   -  FF refers to the layers which are floating.
+   -  VVVVV refers to the "variant" when there are multiple devices of the same configuration
+
+Operating Voltages where SPICE models are valid
+
+-  \|V\ :sub:`c0` – V\ :sub:`c1`\ \| = 0 to 5.5V
+
+Details
+~~~~~~~
+
+The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below:
+
+.. todo::
+
+    M3
+
+    **M2**
+
+    LI
+
+    M1
+
+    LAYOUT of M2, M3, M4
+
+    LAYOUT of LI and M1 (with POLY sheet)
+
+    **POLY**
+
+    **M4**
+
+These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions.
+
+Parallel VPP Capacitors
+^^^^^^^^^^^^^^^^^^^^^^^
+
+These are older versions, where stacked metal lines run parallel:
+
+
+-  :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield` (M1 \|\| M2 only, 7.84 x 8.58)
+-  :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2` (M1 \|\| M2 only, 4.38 x 4.59)
+-  :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield` (M1 \|\| M2 only, 2.19 x 4.59)
+-  :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield` (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants)
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield` (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants)
+-  :model:`sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield`
+-  :model:`sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0)
+-  :model:`sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2` (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0)
+-  :model:`sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0)
+-  :model:`sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0)
+-  :model:`sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0)
+
+The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well).
+
+|symbol-cap_vpp-parallel|
+
+Perpendicular VPP Capacitors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom:
+
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5` (11.5x11.7, with M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5` (11.5x11.7, with poly and M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5` (11.5x11.7, with LI and M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4` (4.4x4.6, M3 float, LI / M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4` (8.6x7.9, M3 float, LI / M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4` (11.5x11.7, M3 float, LI / M5 shield)
+-  :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4` (11.5x11.7, with M4 shield)
+-  :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4` (6.8x6.1, with poly and M4 shield)
+-  :model:`sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4` (6.8x6.1, with LI and M4 shield)
+-  :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5` (11.5x11.7, over 2 :model:`sky130_fd_pr__nfet_05v0_nvt` of 10/4 each)
+
+The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield.
+
+|symbol-cap_vpp-perpendicular|
+
+The capacitors are fixed-size elements and must be used as-is; they can be used in multiples.
+
+
+.. include:: cap_vpp-table0.rst
+
+.. |symbol-cap_vpp-parallel| image:: symbol-cap_vpp-parallel.svg
+.. |symbol-cap_vpp-perpendicular| image:: symbol-cap_vpp-perpendicular.svg

docs/rules/device-details/capacitors-vpp/index.rst

@@ -1,88 +0,0 @@
-Vertical Parallel Plate (VPP) capacitors
-----------------------------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__cap_int3_vppcap`
--  Model Names: :model:`sky130_fd_pr_base__xcmvppXxY _{MMshield}`
-
-   -  X and Y are size dimentions
-   -  {MMshield} refers to metal layer used as shield
-
-Operating Voltages where SPICE models are valid
-
--  \|V\ :sub:`c0` – V\ :sub:`c1`\ \| = 0 to 5.5V
-
-Details
-~~~~~~~
-
-The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below:
-
-M3
-
-**M2**
-
-LI
-
-M1
-
-LAYOUT of M2, M3, M4
-
-LAYOUT of LI and M1 (with POLY sheet)
-
-**POLY**
-
-**M4**
-
-These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are multiple constructions under two different cell names:
-
-cap\_int3—these are older versions, where stacked metal lines run parallel
-
--  xcmvpp3 (M1 \|\| M2 only, 7.84 x 8.58)
--  xcmvpp4 (M1 \|\| M2 only, 4.38 x 4.59)
--  xcmvpp5 (M1 \|\| M2 only, 2.19 x 4.59)
--  xcmvpp4p4x4p6\_m1m2 (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants)
--  xcmvpp11p5x11p7\_m1m2 (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants)
--  xcmvpp\_hd5\_4x2
--  xcmvpp\_hd5\_atlas\_fingercap\_l5 (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0)
--  xcmvpp\_hd5\_atlas\_fingercap2\_l5 (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0)
--  xcmvpp\_hd5\_atlas\_fingercap\_l10 (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0)
--  xcmvpp\_hd5\_atlas\_fingercap\_l20 (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0)
--  xcmvpp\_hd5\_atlas\_fingercap\_l40 (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0)
-
-The symbol for the cap\_int3 is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well).
-
-|symbol-capacitor-vpp-cap_int3|
-
-cap\_int3
-
-vppcap—newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom
-
--  xcmvpp11p5x11p7\_m5shield (11.5x11.7, with M5 shield)
--  xcmvpp11p5x11p7\_polym5shield (11.5x11.7, with poly and M5 shield)
--  xcmvpp11p5x11p7\_lim5shield (11.5x11.7, with LI and M5 shield)
--  xcmvpp4p4x4p6\_m3\_lim5shield (4.4x4.6, M3 float, LI / M5 shield)
--  xcmvpp8p6x7p9\_m3\_lim5shield (8.6x7.9, M3 float, LI / M5 shield)
--  xcmvpp11p5x11p7\_m3\_lim5shield (11.5x11.7, M3 float, LI / M5 shield)
--  xcmvpp11p5x11p7\_m4shield (11.5x11.7, with M4 shield)
--  xcmvpp6p8x6p1\_polym4shield (6.8x6.1, with poly and M4 shield)
--  xcmvpp6p8x6p1\_lim4shield (6.8x6.1, with LI and M4 shield)
--  xcmvppx4x2xnhative10x4 (11.5x11.7, over 2 nhvnative of 10/4 each)
-
-The symbol for the vppcap is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield.
-
-|symbol-capacitor-vpp-cap|
-
-The capacitors are fixed-size elements and must be used as-is; they can be used in multiples.
-
-
-.. include:: capacitors-vpp-table0.rst
-
-
-
-This page intentionally left blank
-
-.. |symbol-capacitor-vpp-cap_int3| image:: symbol-capacitor-vpp-cap_int3.svg
-.. |symbol-capacitor-vpp-cap| image:: symbol-capacitor-vpp-cap.svg
-

docs/rules/device-details/diodes/index.rst

@@ -4,10 +4,10 @@ Diodes
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__diode`
--  Model Names: :model:`sky130_fd_pr_base__ndiode`, :model:`sky130_fd_pr_base__ndiode_h`, :model:`sky130_fd_pr_base__ndiode_native`, :model:`sky130_fd_pr_base__ndiode_lvt`, :model:`sky130_fd_pr_base__pdiode`, :model:`sky130_fd_pr_base__pdiode_h`, :model:`sky130_fd_pr_base__pdiode_hvt`, :model:`sky130_fd_pr_base__pdiode_lvt`, :model:`sky130_fd_pr_base__xnwdiode_rf`, :model:`sky130_fd_pr_base__xdnwdiode_pwell_rf`, :model:`sky130_fd_pr_base__dnwdiode_pw`, :model:`sky130_fd_pr_base__dnwdiode_psub`, :model:`sky130_fd_pr_base__dnwdiode_psub_victim`, :model:`sky130_fd_pr_base__dnwdiode_psub_aggressor`, :model:`sky130_fd_pr_base__nwdiode`, :model:`sky130_fd_pr_base__nwdiode_victim`, :model:`sky130_fd_pr_base__nwdiode_aggressor`, :model:`sky130_fd_pr_base__xesd_ndiode_h_X`, :model:`sky130_fd_pr_base__xesd_ndiode_h_dnwl_X`, :model:`sky130_fd_pr_base__xesd_pdiode_h_X (X = 100 or 200 or 300)`
--  Cell Name: :cell:`sky130_fd_pr_base__lvsdiode`
--  Model Names: :model:`sky130_fd_pr_base__ndiode`, :model:`sky130_fd_pr_base__ndiode_h`, :model:`sky130_fd_pr_base__pdiode`, :model:`sky130_fd_pr_base__pdiode_h`, :model:`sky130_fd_pr_base__dnwdiode_psub`, :model:`sky130_fd_pr_base__dnwdiode_psub_victim`, :model:`sky130_fd_pr_base__dnwdiode_psub_aggressor`, :model:`sky130_fd_pr_base__nwdiode_victim`, :model:`sky130_fd_pr_base__nwdiode_aggressor`, :model:`sky130_fd_pr_base__xesd_ndiode_h_X`, :model:`sky130_fd_pr_base__xesd_ndiode_h_dnwl_X`, :model:`sky130_fd_pr_base__xesd_pdiode_h_X (X = 100 or 200 or 300)`
+-  Cell Name: :cell:`diode`
+-  Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pw2nd_05v5_nvt`, :model:`sky130_fd_pr__diode_pw2nd_05v5_lvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5_hvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5_lvt`, :model:`sky130_fd_pr__model__parasitic__rf_diode_ps2nw`, :model:`sky130_fd_pr__model__parasitic__rf_diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`sky130_fd_pr__model__parasitic__diode_ps2nw`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
+-  Cell Name: :cell:`lvsdiode`
+-  Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)`
 
 Operating regime where SPICE models are valid
 
@@ -23,17 +23,23 @@ Details
 
 Symbols for the diodes are shown below
 
-|symbol-diode-01|\ |symbol-diode-02|\ |symbol-diode-03|\ |symbol-diode-04|
-
-|symbol-diode-05| |symbol-diode-06| |symbol-diode-07| |symbol-diode-08|
-
-|symbol-diode-09| |symbol-diode-10| |symbol-diode-11|
-
-|symbol-diode-12| |symbol-diode-13|
-
-|symbol-diode-14| |symbol-diode-15|
-
-|symbol-diode-16| |symbol-diode-17|
+|symbol-diode-01|
+|symbol-diode-02|
+|symbol-diode-03|
+|symbol-diode-04|
+|symbol-diode-05|
+|symbol-diode-06|
+|symbol-diode-07|
+|symbol-diode-08|
+|symbol-diode-09|
+|symbol-diode-10|
+|symbol-diode-11|
+|symbol-diode-12|
+|symbol-diode-13|
+|symbol-diode-14|
+|symbol-diode-15|
+|symbol-diode-16|
+|symbol-diode-17|
 
 .. |symbol-diode-01| image:: symbol-diode-01.svg
 .. |symbol-diode-02| image:: symbol-diode-02.svg

docs/rules/device-details/esd_nfet/index.rst

@@ -0,0 +1,43 @@
+NMOS ESD FET
+------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+-  V\ :sub:`GS` = 0 to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+-  V\ :sub:`BS` = 0 to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`)
+
+Details
+~~~~~~~
+
+The ESD FET’s differ from the regular NMOS devices in several aspects, most notably:
+
+-  Increased isolation spacing from contacts to surrounding STI
+-  Increased drain contact-to-gate spacing
+-  Placement of n-well under the drain contacts
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: esd_nfet-table0.rst
+
+
+
+The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below:
+
+|symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt|
+
+The cross-section of the ESD NMOS FET is shown below.
+
+|cross-section-esd_nfet|
+
+.. |symbol-esd_nfet_g5v0d10v5| image:: symbol-esd_nfet_g5v0d10v5.svg
+.. |symbol-esd_nfet_g5v0d10v5_nvt| image:: symbol-esd_nfet_g5v0d10v5_nvt.svg
+.. |cross-section-esd_nfet| image:: cross-section-esd_nfet.svg
+

docs/rules/device-details/fet-nmos-1v8-low-vt/index.rst

@@ -1,43 +0,0 @@
-1.8V low-VT NMOS FET
---------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__nlowvt`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to 1.95V
--  V\ :sub:`GS` = 0 to 1.95V
--  V\ :sub:`BS` = +0.3 to -1.95V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs.
-
-
-.. include:: fet-nmos-1v8-low-vt-table0.rst
-
-
-
-Inverter Gate Delays using :model:`sky130_fd_pr_base__nlowvt`/pshort device combinations:
-
-
-.. include:: fet-nmos-1v8-low-vt-table1.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr_base__nlowvt` (1.8V low-VT NMOS FET) is shown below:
-
-|symbol-1v8-low-vt-nmos-fet|
-
-The cross-section of the low-VT NMOS FET is shown below. The cross-section is identical to the std NMOS FET except for the V\ :sub:`T` adjust implants (to achieve the lower V\ :sub:`T`)
-
-|cross-section-1v8-low-vt-nmos-fet|
-
-.. |symbol-1v8-low-vt-nmos-fet| image:: symbol-1v8-low-vt-nmos-fet.svg
-.. |cross-section-1v8-low-vt-nmos-fet| image:: cross-section-1v8-low-vt-nmos-fet.svg
-

docs/rules/device-details/fet-nmos-3v0-native/index.rst

@@ -1,40 +0,0 @@
-3.0V native NMOS FET
---------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__ntvnative`
-
-Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr_base__ntvnative`
-
--  V\ :sub:`DS` = 0 to 3.3V
--  V\ :sub:`GS` = 0 to 3.3V
--  V\ :sub:`BS` = 0 to -3.3V
-
-Details
-~~~~~~~
-
-The native device is constructed by blocking out all VT implants.
-
-The model and EDR (e-test) parameters are compared below. Note that the minimum gate length for 3V operation is 0.5 µm.
-
-
-.. include:: ../fet-nmos-3v0-and-5v0-native/fet-nmos-3v0-and-5v0-native-table0.rst
-
-
-
-The symbols for the :model:`sky130_fd_pr_base__ntvnative` devices are shown below.
-
-|symbol-3v0-native-nmos-fet-ntvnative|
-
-The cross-section of the native devices is shown below.
-
-
-|cross-section-3v0-and-5v0-native-nmos-fet|
-
-.. |symbol-3v0-native-nmos-fet-ntvnative| image:: symbol-3v0-nmos-fet-ntvnative.svg
-.. |cross-section-3v0-and-5v0-native-nmos-fet| image:: cross-section-3v0-and-5v0-native-nmos-fet.svg
-
-.. note:: The only differences between the :model:`sky130_fd_pr_base__nvtnative` and :model:`sky130_fd_pr_base__nhvnative` devices are the minimum gate length and the VDS requirements.

docs/rules/device-details/fet-nmos-5v0-10v5/index.rst

@@ -1,36 +0,0 @@
-5.0V/10.5V NMOS FET
--------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__nhv`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to 11.0V
--  V\ :sub:`GS` = 0 to 5.5V
--  V\ :sub:`BS` = 0 to -5.5V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: fet-nmos-5v0-10v5-table0.rst
-
-
-
-The symbols of the :model:`sky130_fd_pr_base__nhv` (5.0/10.5 V NMOS FET) is shown below:
-
-|symbol-5v0-10v5-nmos-fet|
-
-The cross-section of the 5.0/10.5 V NMOS FET is shown below.
-
-|cross-section-5v0-10v5-nmos-fet|
-
-.. |symbol-5v0-10v5-nmos-fet| image:: symbol-5v0-10v5-nmos-fet.svg
-.. |cross-section-5v0-10v5-nmos-fet| image:: cross-section-5v0-10v5-nmos-fet.svg
-

docs/rules/device-details/fet-nmos-5v0-native/index.rst

@@ -1,41 +0,0 @@
-5.0V native NMOS FET
---------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__nhvnative`
-
-Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr_base__nhvnative`
-
--  V\ :sub:`DS` = 0 to 5.5V
--  V\ :sub:`GS` = 0 to 5.5V
--  V\ :sub:`BS` = +0.3 to -5.5V
-
-Details
-~~~~~~~
-
-The native device is constructed by blocking out all VT implants.
-
-The model and EDR (e-test) parameters are compared below.
-
-The 5V device has minimum gate length of 0.9 µm.
-
-
-.. include:: ../fet-nmos-3v0-and-5v0-native/fet-nmos-3v0-and-5v0-native-table0.rst
-
-
-The symbols for the :model:`sky130_fd_pr_base__nhvnative` devices are shown below.
-
-|symbol-5v0-native-nmos-fet-nhvnative|
-
-The cross-section of the native devices is shown below.
-
-.. note:: The only differences between the :model:`sky130_fd_pr_base__nvtnative` and :model:`sky130_fd_pr_base__nhvnative` devices are the minimum gate length and the VDS requirements.
-
-|cross-section-3v0-and-5v0-native-nmos-fet|
-
-.. |symbol-5v0-native-nmos-fet-nhvnative| image:: symbol-5v0-native-nmos-fet-nhvnative.svg
-.. |cross-section-3v0-and-5v0-native-nmos-fet| image:: ../fet-nmos-3v0-and-5v0-native/cross-section-3v0-and-5v0-native-nmos-fet.svg
-

docs/rules/device-details/fet-nmos-esd/index.rst

@@ -1,43 +0,0 @@
-NMOS ESD FET
-------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__nshortesd`, :model:`sky130_fd_pr_base__nhvesd`, :model:`sky130_fd_pr_base__nhvesdnative`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to 11.0V (nhv\*), 0 to 1.95V (nshort\*)
--  V\ :sub:`GS` = 0 to 5.0V (nhv\*), 0 to 1.95V (nshort\*)
--  V\ :sub:`BS` = 0 to -5.5V, (nhv), +0.3 to -5.5V (nhvnative), 0 to -1.95V (nshort\*)
-
-Details
-~~~~~~~
-
-The ESD FET’s differ from the regular NMOS devices in several aspects, most notably:
-
--  Increased isolation spacing from contacts to surrounding STI
--  Increased drain contact-to-gate spacing
--  Placement of n-well under the drain contacts
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: fet-nmos-esd-table0.rst
-
-
-
-The symbols of the :model:`sky130_fd_pr_base__nhvesd` and :model:`sky130_fd_pr_base__nhvesdnative` (ESD NMOS FET) are shown below:
-
-|symbol-nmos-esd-fet-nhvesd| |symbol-nmos-esd-fet-nhvesdnative|
-
-The cross-section of the ESD NMOS FET is shown below.
-
-|cross-section-nmos-esd-fet|
-
-.. |symbol-nmos-esd-fet-nhvesd| image:: symbol-nmos-esd-fet-nhvesd.svg
-.. |symbol-nmos-esd-fet-nhvesdnative| image:: symbol-nmos-esd-fet-nhvesdnative.svg
-.. |cross-section-nmos-esd-fet| image:: cross-section-nmos-esd-fet.svg
-

docs/rules/device-details/fet-pmos-1v8-high-vt/index.rst

@@ -1,43 +0,0 @@
-1.8V high-VT PMOS FET
----------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__pfet`
--  Model Name: :model:`sky130_fd_pr_base__phighvt`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to -1.95V
--  V\ :sub:`GS` = 0 to -1.95V
--  V\ :sub:`BS` = -0.1 to +1.95V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: fet-pmos-1v8-high-vt-table0.rst
-
-
-
-Inverter Gate Delays using nshort/:model:`sky130_fd_pr_base__phighvt` device combinations:
-
-
-.. include:: fet-pmos-1v8-high-vt-table1.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr_base__phighvt` (1.8V high-VT PMOS FET) is shown below:
-
-|symbol-1v8-high-vt-pmos-fet|
-
-The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the V\ :sub:`T` adjust implants (to achieve the higher V\ :sub:`T`)
-
-|cross-section-1v8-high-vt-pmos-fet|
-
-.. |symbol-1v8-high-vt-pmos-fet| image:: symbol-1v8-high-vt-pmos-fet.svg
-.. |cross-section-1v8-high-vt-pmos-fet| image:: cross-section-1v8-high-vt-pmos-fet.svg
-

docs/rules/device-details/fet-pmos-1v8-low-vt/index.rst

@@ -1,43 +0,0 @@
-1.8V low-VT PMOS FET
---------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__pfet`
--  Model Name: :model:`sky130_fd_pr_base__plowvt`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to -1.95V
--  V\ :sub:`GS` = 0 to -1.95V
--  V\ :sub:`BS` = -0.1 to +1.95V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: fet-pmos-1v8-low-vt-table0.rst
-
-
-
-Inverter Gate Delays using nlowvt/:model:`sky130_fd_pr_base__plowvt` device combinations:
-
-
-.. include:: fet-pmos-1v8-low-vt-table1.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr_base__plowvt` (1.8V low-VT PMOS FET) is shown below:
-
-|symbol-1v8-low-vt-pmos-fet|
-
-The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the V\ :sub:`T` adjust implants (to achieve the lower V\ :sub:`T`)
-
-|cross-section-1v8-low-vt-pmos-fet|
-
-.. |symbol-1v8-low-vt-pmos-fet| image:: symbol-1v8-low-vt-pmos-fet.svg
-.. |cross-section-1v8-low-vt-pmos-fet| image:: cross-section-1v8-low-vt-pmos-fet.svg
-

docs/rules/device-details/fet-pmos-1v8/index.rst

@@ -1,43 +0,0 @@
-1.8V PMOS FET
--------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__pfet`
--  Model Name: :model:`sky130_fd_pr_base__pshort`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to -1.95V
--  V\ :sub:`GS` = 0 to -1.95V
--  V\ :sub:`BS` = -0.1 to +1.95V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs.
-
-
-.. include:: fet-pmos-1v8-table0.rst
-
-
-
-Inverter Gate Delays using nshort/:model:`sky130_fd_pr_base__pshort` device combinations:
-
-
-.. include:: fet-pmos-1v8-table1.rst
-
-
-
-The symbol of the :model:`sky130_fd_pr_base__pshort` (1.8V PMOS FET) is shown below:
-
-|symbol-1v8-pmos-fet|
-
-The cross-section of the PMOS FET is shown below:
-
-|cross-section-1v8-pmos-fet|
-
-.. |symbol-1v8-pmos-fet| image:: symbol-1v8-pmos-fet.svg
-.. |cross-section-1v8-pmos-fet| image:: cross-section-1v8-pmos-fet.svg
-

docs/rules/device-details/fet-pmos-5v0-10v5/index.rst

@@ -1,44 +0,0 @@
-5.0V/10.5V PMOS FET
--------------------
-
-Spice Model Information
-~~~~~~~~~~~~~~~~~~~~~~~
-
--  Cell Name: :cell:`sky130_fd_pr_base__pfet`
--  Model Name: :model:`sky130_fd_pr_base__phv`, :model:`sky130_fd_pr_base__phvesd`
-
-Operating Voltages where SPICE models are valid
-
--  V\ :sub:`DS` = 0 to -11.0V
--  V\ :sub:`GS` = 0 to -5.5V
--  V\ :sub:`BS` = 0 to +5.5V
-
-Details
-~~~~~~~
-
-Major model output parameters are shown below and compared against the EDR (e-test) specs
-
-
-.. include:: fet-pmos-5v0-10v5-table0.rst
-
-
-
-Inverter gate delays are shown below:
-
-
-.. include:: fet-pmos-5v0-10v5-table1.rst
-
-
-
-The symbols of the :model:`sky130_fd_pr_base__phv` and pvhesd (5.0V/10.5V PMOS FET) are shown below:
-
-|symbol-5v0-10v5-pmos-fet-phv| |symbol-5v0-10v5-pmos-fet-pvhesd|
-
-The cross-section of the 5.0V PMOS FET is shown below.
-
-|cross-section-5v0-10v5-pmos-fet|
-
-.. |symbol-5v0-10v5-pmos-fet-phv| image:: symbol-5v0-10v5-pmos-fet-phv.svg
-.. |symbol-5v0-10v5-pmos-fet-pvhesd| image:: symbol-5v0-10v5-pmos-fet-pvhesd.svg
-.. |cross-section-5v0-10v5-pmos-fet| image:: cross-section-5v0-10v5-pmos-fet.svg
-

docs/rules/device-details/nfet_01v8/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfet`
--  Model Name: :model:`sky130_fd_pr_base__nshort`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__nfet_01v8`
 
 Operating Voltages where SPICE models are valid
 
@@ -19,20 +19,20 @@ Details
 Major model output parameters are shown below and compared against the EDR (e-test) specs.
 
 
-.. include:: fet-nmos-1v8-table0.rst
+.. include:: nfet_01v8-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__nshort` (1.8V NMOS FET) is shown below:
+The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below:
 
-|symbol-1v8-nmos-fet|
+|symbol-nfet_01v8|
 
 The cross-section of the NMOS FET is shown below:
 
-|cross-section-1v8-nmos-fet|
+|cross-section-nfet_01v8|
 
 The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well
 
-.. |symbol-1v8-nmos-fet| image:: symbol-1v8-nmos-fet.svg
-.. |cross-section-1v8-nmos-fet| image:: cross-section-1v8-nmos-fet.svg
+.. |symbol-nfet_01v8| image:: symbol-nfet_01v8.svg
+.. |cross-section-nfet_01v8| image:: cross-section-nfet_01v8.svg
 

docs/rules/device-details/nfet_01v8_lvt/index.rst

@@ -0,0 +1,43 @@
+1.8V low-VT NMOS FET
+--------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__nfet_01v8_lvt`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to 1.95V
+-  V\ :sub:`GS` = 0 to 1.95V
+-  V\ :sub:`BS` = +0.3 to -1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs.
+
+
+.. include:: nfet_01v8_lvt-table0.rst
+
+
+
+Inverter Gate Delays using :model:`sky130_fd_pr__nfet_01v8_lvt`/:model:`sky130_fd_pr__pfet_01v8` device combinations:
+
+
+.. include:: nfet_01v8_lvt-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__nfet_01v8_lvt` (1.8V low-VT NMOS FET) is shown below:
+
+|symbol-nfet_01v8_lvt|
+
+The cross-section of the low-VT NMOS FET is shown below. The cross-section is identical to the std NMOS FET except for the V\ :sub:`T` adjust implants (to achieve the lower V\ :sub:`T`)
+
+|cross-section-nfet_01v8_lvt|
+
+.. |symbol-nfet_01v8_lvt| image:: symbol-nfet_01v8_lvt.svg
+.. |cross-section-nfet_01v8_lvt| image:: cross-section-nfet_01v8_lvt.svg
+

docs/rules/device-details/nfet_01v8_lvt/nfet_01v8_lvt-table1.rst

@@ -9,7 +9,6 @@
      - MODEL
      - 
      - 
-     - 
      - EDR
      - 
      - 

docs/rules/device-details/nfet_03v3_nvt/index.rst

@@ -0,0 +1,40 @@
+3.0V native NMOS FET
+--------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__nfet_03v3_nvt`
+
+Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_03v3_nvt`
+
+-  V\ :sub:`DS` = 0 to 3.3V
+-  V\ :sub:`GS` = 0 to 3.3V
+-  V\ :sub:`BS` = 0 to -3.3V
+
+Details
+~~~~~~~
+
+The native device is constructed by blocking out all VT implants.
+
+The model and EDR (e-test) parameters are compared below. Note that the minimum gate length for 3V operation is 0.5 µm.
+
+
+.. include:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst
+
+
+
+The symbols for the :model:`sky130_fd_pr__nfet_03v3_nvt` devices are shown below.
+
+|symbol-nfet_0v3v3_nvt|
+
+The cross-section of the native devices is shown below.
+
+
+|cross-section-nfet_03v3_nvt|
+
+.. |symbol-nfet_0v3v3_nvt| image:: symbol-nfet_03v3_nvt.svg
+.. |cross-section-nfet_03v3_nvt| image:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg
+
+.. note:: The only differences between the :model:`sky130_fd_pr__nfet_03v3_nvt` and :model:`sky130_fd_pr__nfet_05v0_nvt` devices are the minimum gate length and the VDS requirements.

docs/rules/device-details/nfet_05v0_nvt/index.rst

@@ -0,0 +1,41 @@
+5.0V native NMOS FET
+--------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt`
+
+Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt`
+
+-  V\ :sub:`DS` = 0 to 5.5V
+-  V\ :sub:`GS` = 0 to 5.5V
+-  V\ :sub:`BS` = +0.3 to -5.5V
+
+Details
+~~~~~~~
+
+The native device is constructed by blocking out all VT implants.
+
+The model and EDR (e-test) parameters are compared below.
+
+The 5V device has minimum gate length of 0.9 µm.
+
+
+.. include:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/nfet_03v3_nvt-and-nfet_05v0_nvt-table0.rst
+
+
+The symbols for the :model:`sky130_fd_pr__nfet_05v0_nvt` devices are shown below.
+
+|symbol-nfet_05v0_nvt|
+
+The cross-section of the native devices is shown below.
+
+.. note:: The only differences between the :model:`sky130_fd_pr__nfet_03v3_nvt` and :model:`sky130_fd_pr__nfet_05v0_nvt` devices are the minimum gate length and the VDS requirements.
+
+|cross-section-nfet_05v0_nvt|
+
+.. |symbol-nfet_05v0_nvt| image:: symbol-nfet_05v0_nvt.svg
+.. |cross-section-nfet_05v0_nvt| image:: ../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg
+

docs/rules/device-details/nfet_20v0/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfetexd`
--  Model Name: :model:`sky130_fd_pr_base__n20vhv1`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_20v0`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -26,18 +26,18 @@ The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-nmos-20v-table0.rst
+.. include:: nfet_20v0-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__n20vhv1` (20V NMOS FET) is shown below.
+The symbol of the :model:`sky130_fd_pr__nfet_20v0` (20V NMOS FET) is shown below.
 
-|symbol-20v-nmos-fet|
+|symbol-nfet_20v0|
 
 The cross-section of the 20V NMOS FET is shown below.
 
-|cross-section-20v-nmos-fet|
+|cross-section-nfet_20v0|
 
-.. |symbol-20v-nmos-fet| image:: symbol-20v-nmos-fet.svg
-.. |cross-section-20v-nmos-fet| image:: cross-section-20v-nmos-fet.svg
+.. |symbol-nfet_20v0| image:: symbol-nfet_20v0.svg
+.. |cross-section-nfet_20v0| image:: cross-section-nfet_20v0.svg
 

docs/rules/device-details/nfet_20v0_iso/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfetexd`
--  Model Name: :model:`sky130_fd_pr_base__n20vhviso1`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_20v0_iso`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -21,18 +21,18 @@ The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-nmos-20v-isolated-table0.rst
+.. include:: nfet_20v0_iso-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__n20vhviso1` (20V isolated NMOS FET) is shown below.
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below.
 
-|symbol-20v-isolated-nmos-fet|
+|symbol-nfet_20v0_iso|
 
 The cross-section of the 20V isolated NMOS FET is shown below.
 
-|cross-section-20v-isolated-nmos-fet|
+|cross-section-nfet_20v0_iso|
 
-.. |symbol-20v-isolated-nmos-fet| image:: symbol-20v-isolated-nmos-fet.svg
-.. |cross-section-20v-isolated-nmos-fet| image:: cross-section-20v-isolated-nmos-fet.svg
+.. |symbol-nfet_20v0_iso| image:: symbol-nfet_20v0_iso.svg
+.. |cross-section-nfet_20v0_iso| image:: cross-section-nfet_20v0_iso.svg
 

docs/rules/device-details/nfet_20v0_nvt/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfetexd`
--  Model Name: :model:`sky130_fd_pr_base__n20nativevhv1`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_20v0_nvt`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -21,18 +21,18 @@ The 20V native NMOS FET is similar to the 20V isolated NMOS FET, but has all Vt
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-nmos-20v-native-table0.rst
+.. include:: nfet_20v0_nvt-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__n20nativevhv1` (20V native NMOS FET) shown below.
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_nvt` (20V native NMOS FET) shown below.
 
-|symbol-20v-native-nmos-fet|
+|symbol-nfet_20v0_nvt|
 
 The cross-section of the 20V native NMOS FET is shown below.
 
-|cross-section-20v-native-nmos-fet|
+|cross-section-nfet_20v0_nvt|
 
-.. |symbol-20v-native-nmos-fet| image:: symbol-20v-native-nmos-fet.svg
-.. |cross-section-20v-native-nmos-fet| image:: cross-section-20v-native-nmos-fet.svg
+.. |symbol-nfet_20v0_nvt| image:: symbol-nfet_20v0_nvt.svg
+.. |cross-section-nfet_20v0_nvt| image:: cross-section-nfet_20v0_nvt.svg
 

docs/rules/device-details/nfet_20v0_zvt/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfetexd`
--  Model Name: :model:`sky130_fd_pr_base__n20zvtvhv1`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_20v0_zvt`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -21,15 +21,15 @@ The 20V NMOS zero-VT FET has p-well and all Vt implants blocked to achieve a zer
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-nmos-20v-zero-vt-table0.rst
+.. include:: nfet_20v0_zvt-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__n20zvtvhv1` (20V NMOS zero-VT FET) is still under development.
+The symbol of the :model:`sky130_fd_pr__nfet_20v0_zvt` (20V NMOS zero-VT FET) is still under development.
 
 The cross-section of the 20V NMOS zero-VT FET is shown below.
 
-|cross-section-20v-nmos-zero-vt-fet|
+|cross-section-nfet_20v0_zvt|
 
-.. |cross-section-20v-nmos-zero-vt-fet| image:: cross-section-20v-nmos-zero-vt-fet.svg
+.. |cross-section-nfet_20v0_zvt| image:: cross-section-nfet_20v0_zvt.svg
 

docs/rules/device-details/nfet_g11v0d16v0/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__nfetexd`
--  Model Name: :model:`sky130_fd_pr_base__nvhv`
+-  Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -20,18 +20,18 @@ Details
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-nmos-11v-16v-table0.rst
+.. include:: nfet_g11v0d16v0-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__nvhv` (11V/16V NMOS FET) is shown below:
+The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below:
 
-|symbol-11v-16v-nmos-fet|
+|symbol-nfet_g11v0d16v0|
 
 The cross-section of the 11V/16VV NMOS FET is shown below.
 
-|cross-section-11v-16v-nmos-fet|
+|cross-section-nfet_g11v0d16v0|
 
-.. |symbol-11v-16v-nmos-fet| image:: symbol-11v-16v-nmos-fet.svg
-.. |cross-section-11v-16v-nmos-fet| image:: cross-section-11v-16v-nmos-fet.svg
+.. |symbol-nfet_g11v0d16v0| image:: symbol-nfet_g11v0d16v0.svg
+.. |cross-section-nfet_g11v0d16v0| image:: cross-section-nfet_g11v0d16v0.svg
 

docs/rules/device-details/nfet_g5v0d10v5/index.rst

@@ -0,0 +1,36 @@
+5.0V/10.5V NMOS FET
+-------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__nfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to 11.0V
+-  V\ :sub:`GS` = 0 to 5.5V
+-  V\ :sub:`BS` = 0 to -5.5V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: nfet_g5v0d10v5-table0.rst
+
+
+
+The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below:
+
+|symbol-nfet_g5v0d10v5|
+
+The cross-section of the 5.0/10.5 V NMOS FET is shown below.
+
+|cross-section-nfet_g5v0d10v5|
+
+.. |symbol-nfet_g5v0d10v5| image:: symbol-nfet_g5v0d10v5.svg
+.. |cross-section-nfet_g5v0d10v5| image:: cross-section-nfet_g5v0d10v5.svg
+

docs/rules/device-details/npn_05v0/index.rst

@@ -0,0 +1,51 @@
+Bipolar (NPN)
+-------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__npn_05v5`
+-  Model Names: :model:`sky130_fd_pr__npn_05v5`, :model:`sky130_fd_pr__npn_11v0`
+
+Operating regime where SPICE models are valid
+
+-  \|V\ :sub:`CE`\ \| = 0 to 5.0V
+-  \|V\ :sub:`BE`\ \| = 0 to 5.0V
+-  I\ :sub:`CE` = 0.01 to 10 µA/µm\ :sup:`2`
+
+Details
+~~~~~~~
+
+The SKY130 process offers “free” NPN devices. The NPN uses the deep n-well as the collector. The device is not optimized, and must be used in the forward-active mode. The following sizes of NPN’s are available:
+
+-  ungated device with emitter 1.0 x 1.0
+-  ungated device with emitter 1.0 x 2.0
+-  poly-gated version with octagonal emitter of A = 1.97 µm\ :sup:`2`
+
+The :model:`sky130_fd_pr__npn_11v0` device has a poly gate placed between the emitter and base diffusions, to prevent carrier recombination at the STI edge and increase β. The poly gate is connected to the emitter terminal.
+
+Using this device must be done in conjunction with the correct guard rings, to avoid potential latchup issues with nearby circuitry. Reverse-active mode operation of the BJT’s are neither modeled nor permitted. E-test specs for the NPN devices are shown in the table below:
+
+
+.. include:: npn_05v0-table0.rst
+
+
+
+Symbols for the :model:`sky130_fd_pr__npn_05v5` are shown below
+
+|symbol-npn_05v0-1| |symbol-npn_05v0-2| |symbol-npn_05v0-3|
+
+The cross-section of the :model:`sky130_fd_pr__npn_05v5` is shown below.
+
+|cross-section-npn_05v0|
+
+The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The poly gate is tied to the emitter to prevent the parasitic MOSFET from turning on.
+
+|cross-section-npn_11v0|
+
+.. |symbol-npn_05v0-1| image:: symbol-npn_05v0-1.svg
+.. |symbol-npn_05v0-2| image:: symbol-npn_05v0-2.svg
+.. |symbol-npn_05v0-3| image:: symbol-npn_05v0-3.svg
+.. |cross-section-npn_05v0| image:: cross-section-npn_05v0.svg
+.. |cross-section-npn_11v0| image:: cross-section-npn_11v0.svg
+

docs/rules/device-details/npn_05v0/npn_05v0-table0.rst

@@ -15,42 +15,42 @@
      - 18.14
      - 56.93
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =10 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =10 µA
 
    * - BFNPN1X1\_1P0
      - 36.72
      - 17.97
      - 55.38
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =1.0 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =1.0 µA
 
    * - BFNPN1X2\_17P5
      - 35.14
      - 16.98
      - 53.37
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =17.5 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =17.5 µA
 
    * - BFNPN1X2\_1P75
      - 34.57
      - 16.89
      - 52.2
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =1.75 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =1.75 µA
 
    * - BFNPNPOLY\_3P16
      - 125.28
      - 62.37
      - 500
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =3.16 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =3.16 µA
 
    * - BFNPNPOLY\_P316
      - 106.98
      - 55.94
      - 500
      - 
-     - NPN forward Current Gain (I:sub:`C`/I:sub:`B`) at I\ :sub:`E`\ =0.316 µA
+     - NPN forward Current Gain (I\ :sub:`C`/I\ :sub:`B`) at I\ :sub:`E`\ =0.316 µA
 
    * - VBENPN1X1\_10P0
      - 0.7745

docs/rules/device-details/pfet_01v8/index.rst

@@ -0,0 +1,43 @@
+1.8V PMOS FET
+-------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__pfet_01v8`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to -1.95V
+-  V\ :sub:`GS` = 0 to -1.95V
+-  V\ :sub:`BS` = -0.1 to +1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs.
+
+
+.. include:: pfet_01v8-table0.rst
+
+
+
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations:
+
+
+.. include:: pfet_01v8-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below:
+
+|symbol-pfet_01v8|
+
+The cross-section of the PMOS FET is shown below:
+
+|cross-section-pfet_01v8|
+
+.. |symbol-pfet_01v8| image:: symbol-pfet_01v8.svg
+.. |cross-section-pfet_01v8| image:: cross-section-pfet_01v8.svg
+

docs/rules/device-details/pfet_01v8_hvt/index.rst

@@ -0,0 +1,43 @@
+1.8V high-VT PMOS FET
+---------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to -1.95V
+-  V\ :sub:`GS` = 0 to -1.95V
+-  V\ :sub:`BS` = -0.1 to +1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: pfet_01v8_hvt-table0.rst
+
+
+
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations:
+
+
+.. include:: pfet_01v8_hvt-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below:
+
+|symbol-pfet_01v8_hvt|
+
+The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the V\ :sub:`T` adjust implants (to achieve the higher V\ :sub:`T`)
+
+|cross-section-pfet_01v8_hvt|
+
+.. |symbol-pfet_01v8_hvt| image:: symbol-pfet_01v8_hvt.svg
+.. |cross-section-pfet_01v8_hvt| image:: cross-section-pfet_01v8_hvt.svg
+

docs/rules/device-details/pfet_01v8_lvt/index.rst

@@ -0,0 +1,43 @@
+1.8V low-VT PMOS FET
+--------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to -1.95V
+-  V\ :sub:`GS` = 0 to -1.95V
+-  V\ :sub:`BS` = -0.1 to +1.95V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: pfet_01v8_lvt-table0.rst
+
+
+
+Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations:
+
+
+.. include:: pfet_01v8_lvt-table1.rst
+
+
+
+The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below:
+
+|symbol-pfet_01v8_lvt|
+
+The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the V\ :sub:`T` adjust implants (to achieve the lower V\ :sub:`T`)
+
+|cross-section-pfet_01v8_lvt|
+
+.. |symbol-pfet_01v8_lvt| image:: symbol-pfet_01v8_lvt.svg
+.. |cross-section-pfet_01v8_lvt| image:: cross-section-pfet_01v8_lvt.svg
+

docs/rules/device-details/pfet_20v0/index.rst

@@ -4,8 +4,8 @@
 Spice Model Information
 ~~~~~~~~~~~~~~~~~~~~~~~
 
--  Cell Name: :cell:`sky130_fd_pr_base__pfetexd`
--  Model Name: :model:`sky130_fd_pr_base__p20vhv1`
+-  Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain`
+-  Model Name: :model:`sky130_fd_pr__pfet_20v0`
 
 Operating Voltages where SPICE models are valid, subject to SOA limitations:
 
@@ -26,18 +26,18 @@ The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several
 Major model output parameters are shown below and compared against the EDR (e-test) specs
 
 
-.. include:: fet-pmos-20v-table0.rst
+.. include:: pfet_20v0-table0.rst
 
 
 
-The symbol of the :model:`sky130_fd_pr_base__p20vhv1` (20V PMOS FET) is shown below.
+The symbol of the :model:`sky130_fd_pr__pfet_20v0` (20V PMOS FET) is shown below.
 
-|symbol-20v-pmos-fet|
+|symbol-pfet_20v0|
 
 The cross-section of the 20V PMOS FET is shown below.
 
-|cross-section-20v-pmos-fet|
+|cross-section-pfet_20v0|
 
-.. |symbol-20v-pmos-fet| image:: symbol-20v-pmos-fet.svg
-.. |cross-section-20v-pmos-fet| image:: cross-section-20v-pmos-fet.svg
+.. |symbol-pfet_20v0| image:: symbol-pfet_20v0.svg
+.. |cross-section-pfet_20v0| image:: cross-section-pfet_20v0.svg
 

docs/rules/device-details/pfet_g5v0d10v5/index.rst

@@ -0,0 +1,44 @@
+5.0V/10.5V PMOS FET
+-------------------
+
+Spice Model Information
+~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Cell Name: :cell:`sky130_fd_pr__pfet_01v8`
+-  Model Name: :model:`sky130_fd_pr__pfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_pfet_g5v0d10v5`
+
+Operating Voltages where SPICE models are valid
+
+-  V\ :sub:`DS` = 0 to -11.0V
+-  V\ :sub:`GS` = 0 to -5.5V
+-  V\ :sub:`BS` = 0 to +5.5V
+
+Details
+~~~~~~~
+
+Major model output parameters are shown below and compared against the EDR (e-test) specs
+
+
+.. include:: pfet_g5v0d10v5-table0.rst
+
+
+
+Inverter gate delays are shown below:
+
+
+.. include:: pfet_g5v0d10v5-table1.rst
+
+
+
+The symbols of the :model:`sky130_fd_pr__pfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` (5.0V/10.5V PMOS FET) are shown below:
+
+|symbol-pfet_g5v0d10v5| |symbol-esd_pfet_g5v0d10v5|
+
+The cross-section of the 5.0V PMOS FET is shown below.
+
+|cross-section-pfet_g5v0d10v5|
+
+.. |symbol-pfet_g5v0d10v5| image:: symbol-pfet_g5v0d10v5.svg
+.. |symbol-esd_pfet_g5v0d10v5| image:: symbol-esd_pfet_g5v0d10v5.svg
+.. |cross-section-pfet_g5v0d10v5| image:: cross-section-pfet_g5v0d10v5.svg
+