Improved handling of testbenches with infinite clock
Signed-off-by: Wojciech Gryncewicz <wgryncewicz@antmicro.com>
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@ -75,8 +75,11 @@ def readVCD (file):
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currtag = 'body'
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vcd[currtag] = ''
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if 'var' not in vcd or 'dumpvars' not in vcd:
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raise SyntaxError("Invalid VCD file format")
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if 'var' not in vcd:
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raise SyntaxError("No variables recorded in VCD file")
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if 'dumpvars' not in vcd:
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print ("Warning: intial variable states undefined")
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var['dumpvars'] = ''
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return vcd
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@ -213,9 +216,8 @@ def main():
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svg.saveas(outfile)
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except KeyboardInterrupt:
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sys.exit(1)
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except (AssertionError, FileNotFoundError, ChildProcessError) as ex:
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eprint (f'Error: {type(ex).__name__}')
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eprint (f'{ex.args}')
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except (SyntaxError, AssertionError, FileNotFoundError, ChildProcessError) as ex:
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eprint (f'{type(ex).__name__}: {", ".join(ex.args)}')
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errors +=1
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eprint (f'\n{len(infile)} files processed, {errors} errors.')
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return 0 if errors else 1
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@ -49,6 +49,8 @@ def write_vcd (cellpath, define_data, use_power_pins=False):
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testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v')
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assert os.path.exists(testbedfile), testbedfile
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insertppdefine = use_power_pins
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insertdumpvars = True
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insertfinish = True
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prvline=''
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with open(tmptestbed,'w') as ttb:
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with open(testbedfile,'r') as tbf:
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@ -58,12 +60,17 @@ def write_vcd (cellpath, define_data, use_power_pins=False):
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line = '`define USE_POWER_PINS\n' + line
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insertppdefine = False
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# add dumpfile define
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if prvline.strip(' \n\r')=='begin':
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if insertdumpvars and prvline.strip(' \n\r')=='begin':
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line = line[:-len(line.lstrip())] + \
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'$dumpfile("' + outfile + '");\n' + \
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line[:-len(line.lstrip())] + \
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'$dumpvars(1,top);\n' + \
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line
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insertdumpvars = False
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# add finish command, to stop paraller threads
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if insertfinish and line.strip(' \n\r')=='end' and not '$finish' in prvline:
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line = prvline[:-len(prvline.lstrip())] + '$finish;\n' + line
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insertfinish = False
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# remove power pins from reg - optinal, but makes output more readable
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if not use_power_pins:
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for p in pp:
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