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Improved handling of testbenches with infinite clock 

Signed-off-by: Wojciech Gryncewicz <wgryncewicz@antmicro.com>
This commit is contained in:
Wojciech Gryncewicz 2020-12-01 13:44:17 +01:00
parent c7c5dd8a50
commit adea4260e7
2 changed files with 15 additions and 6 deletions
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12
scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py
View File

@ -75,8 +75,11 @@ def readVCD (file):
currtag = 'body' currtag = 'body'
vcd[currtag] = '' vcd[currtag] = ''
if 'var' not in vcd or 'dumpvars' not in vcd: if 'var' not in vcd:
raise SyntaxError("Invalid VCD file format") raise SyntaxError("No variables recorded in VCD file")
if 'dumpvars' not in vcd:
print ("Warning: intial variable states undefined")
var['dumpvars'] = ''
return vcd return vcd
@ -213,9 +216,8 @@ def main():
svg.saveas(outfile) svg.saveas(outfile)
except KeyboardInterrupt: except KeyboardInterrupt:
sys.exit(1) sys.exit(1)
except (AssertionError, FileNotFoundError, ChildProcessError) as ex: except (SyntaxError, AssertionError, FileNotFoundError, ChildProcessError) as ex:
eprint (f'Error: {type(ex).__name__}') eprint (f'{type(ex).__name__}: {", ".join(ex.args)}')
eprint (f'{ex.args}')
errors +=1 errors +=1
eprint (f'\n{len(infile)} files processed, {errors} errors.') eprint (f'\n{len(infile)} files processed, {errors} errors.')
return 0 if errors else 1 return 0 if errors else 1

9
scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py
View File

@ -49,6 +49,8 @@ def write_vcd (cellpath, define_data, use_power_pins=False):
testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v') testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v')
assert os.path.exists(testbedfile), testbedfile assert os.path.exists(testbedfile), testbedfile
insertppdefine = use_power_pins insertppdefine = use_power_pins
insertdumpvars = True
insertfinish = True
prvline='' prvline=''
with open(tmptestbed,'w') as ttb: with open(tmptestbed,'w') as ttb:
with open(testbedfile,'r') as tbf: with open(testbedfile,'r') as tbf:
@ -58,12 +60,17 @@ def write_vcd (cellpath, define_data, use_power_pins=False):
line = '`define USE_POWER_PINS\n' + line line = '`define USE_POWER_PINS\n' + line
insertppdefine = False insertppdefine = False
# add dumpfile define # add dumpfile define
if prvline.strip(' \n\r')=='begin': if insertdumpvars and prvline.strip(' \n\r')=='begin':
line = line[:-len(line.lstrip())] + \ line = line[:-len(line.lstrip())] + \
'$dumpfile("' + outfile + '");\n' + \ '$dumpfile("' + outfile + '");\n' + \
line[:-len(line.lstrip())] + \ line[:-len(line.lstrip())] + \
'$dumpvars(1,top);\n' + \ '$dumpvars(1,top);\n' + \
line line
insertdumpvars = False
# add finish command, to stop paraller threads
if insertfinish and line.strip(' \n\r')=='end' and not '$finish' in prvline:
line = prvline[:-len(prvline.lstrip())] + '$finish;\n' + line
insertfinish = False
# remove power pins from reg - optinal, but makes output more readable # remove power pins from reg - optinal, but makes output more readable
if not use_power_pins: if not use_power_pins:
for p in pp: for p in pp: