Merge pull request #265 from antmicro/87-cell-waveform-generator
Cell VCD waveform generator script
This commit is contained in:
Ethan Mahintorabi
GitHub
commit
8327221731
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@ -20,6 +20,9 @@ channels:
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dependencies:
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- python=3.8
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- pip
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- yosys
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- netlistsvg
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- iverilog
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# Packages installed from PyPI
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- pip:
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- -r requirements.txt
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@ -1,4 +1,5 @@
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flake8
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wavedrom
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# rst_include tool as GitHub doesn't support `.. include::` when rendering
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# previews.
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@ -0,0 +1,263 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright 2020 The SkyWater PDK Authors.
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#
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# Use of this source code is governed by the Apache 2.0
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# license that can be found in the LICENSE file or at
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# SPDX-License-Identifier: Apache-2.0
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''' VCD waveform to wawedrom script/SVG conversion script.
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'''
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from __future__ import print_function
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import os
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import sys
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import argparse
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import pathlib
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import wavedrom
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import re
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from contextlib import contextmanager
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wavedrom_template ="""\
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{{ signal: [
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{signals}
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]}}"""
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signal_template = " {{ name: \"{name}\", {fill}wave: '{wave}' }}"
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def eprint(*args, **kwargs):
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''' Print to stderr '''
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print(*args, file=sys.stderr, **kwargs)
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@contextmanager
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def file_or_stdout(file):
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''' Open file or stdout if file is None
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'''
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if file is None:
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yield sys.stdout
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else:
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with file.open('w') as out_file:
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yield out_file
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def readVCD (file):
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''' Parses VCD file.
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Args:
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file - path to a VCD file [pathlib.Path]
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Returns:
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vcd - dictionary containing vcd sections [dict]
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'''
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eprint()
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eprint(file.name)
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assert file.is_file(), file
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vcd = {}
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with file.open('r') as f:
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currtag = 'body'
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for line in f:
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# regular line
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if not line.startswith('$'):
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vcd[currtag] = vcd.setdefault(currtag, '') + line
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continue
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# tag, other than end
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if not line.startswith('$end'):
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currtag = line.partition(' ')[0].lstrip('$').rstrip()
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vcd[currtag] = vcd.setdefault(currtag, '') + line.partition(' ')[2].rpartition('$')[0]
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# line ends with end tag
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if not vcd[currtag].endswith('\n'):
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vcd[currtag] += '\n'
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if line.split()[-1]=='$end':
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currtag = 'body'
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vcd[currtag] = ''
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if 'var' not in vcd:
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raise SyntaxError("No variables recorded in VCD file")
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if 'dumpvars' not in vcd:
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print ("Warning: intial variable states undefined")
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var['dumpvars'] = ''
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return vcd
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def reduce_clock_sequences (wave) :
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''' Remove clock seqnces longer than 2 cycles
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not accompanied by other signals changes
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Parameters:
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wave - dictionary 'signal'->['list of states'] [dict]
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'''
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for v in wave:
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sig = wave[v] # analized signal
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other = [wave[i] for i in wave if i!=v] # list of other signals
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other = [''.join(s) for s in zip(*other)] # list of concatenated states
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other = [len(s.replace('.','')) for s in other] # list of state changes count
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sig = [s if o==0 else ' ' for s,o in zip(sig,other)] # keep only when no changes in other
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sig = "".join(sig)
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cuts = []
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for m in re.finditer("(10){2,}",sig):
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cuts.append( (m.start()+1, m.end()-1) ) # area to be reduced, leave 1..0
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cuts.reverse()
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for cut in cuts:
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for v,w in wave.items(): # reduce cuts from all signals
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wave[v] = w[ :cut[0]] + w[cut[1]: ]
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return wave
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def parsetowavedrom (file, savetofile = False, reduce_clock = False):
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''' Reads and simplifies VCD waveform
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Generates wavedrom notation.
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Args:
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file - path to a VCD file [pathlib.Path]
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'''
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varsubst = {} # var substitution
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reg = [] # list of signals
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wire = [] # list of signals (wire class)
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wave = {} # waveform
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event = [] # event timings
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vcd = readVCD (file)
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# parse vars
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for line in vcd['var'].split('\n'):
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line = line.strip().split()
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if len(line)<4:
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if len(line):
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print (f"Warning: malformed var definition {' '.join(line)}")
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continue
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if line[1]!='1':
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print (f"Warning: bus in vars (unsupported) {' '.join(line)}")
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if line[0]=='reg':
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reg.append(line[3])
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varsubst[line[2]] = line[3]
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if line[0]=='wire':
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wire.append(line[3])
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varsubst[line[2]] = line[3]
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# set initial states
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event.append(0)
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#default
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for v in reg+wire:
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wave[v] = ['x']
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#defined
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for line in vcd['dumpvars'].split('\n'):
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if len(line)>=2:
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wave[ varsubst[line[1]] ] = [line[0]]
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# parse wave body
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for line in vcd['body'].split('\n'):
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#timestamp line
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if line.startswith('#'):
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line = line.strip().lstrip('#')
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if not line.isnumeric():
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raise SyntaxError("Invalid VCD timestamp")
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event.append(int(line))
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for v in wave.keys():
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wave[v].append('.')
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# state change line
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else :
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if len(line)>=2:
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wave [ varsubst[line[1]] ][-1] = line[0]
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if reduce_clock:
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wave = reduce_clock_sequences(wave)
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signals = []
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for v in wave.keys():
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fill = ' ' * (max( [len(s) for s in wave.keys()] ) - len(v))
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wavestr = ''.join(wave[v])
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signals.append( signal_template.format( name = v, wave = wavestr, fill = fill ) )
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signals = ',\n'.join(signals)
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wavedrom = wavedrom_template.format ( signals = signals )
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outfile = file.with_suffix(".wdr.json") if savetofile else None
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with file_or_stdout(outfile) as f:
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f.write(wavedrom)
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return wavedrom
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def quoted_strings_wavedrom (wdr) :
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''' Convert wavedrom script to more restrictive
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version of JSON with quoted keywords
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Parameters:
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wdr - wavedrom script [str]
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'''
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wdr = wdr.replace(' signal:',' "signal":')
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wdr = wdr.replace(' name:',' "name":')
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wdr = wdr.replace(' wave:',' "wave":')
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wdr = wdr.replace("'",'"')
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return wdr
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def main():
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''' Converts VCD waveform to wavedrom format'''
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output_txt = 'output:\n stdout or [vcdname].wdr.json file and/or [vcdname].svg file'
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allcellpath = '../../../libraries/*/latest/cells/*/*.vcd'
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parser = argparse.ArgumentParser(
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description = main.__doc__,
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epilog = output_txt,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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parser.add_argument(
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"--all_libs",
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help="process all in "+allcellpath,
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action="store_true")
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parser.add_argument(
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"-w",
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"--wavedrom",
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help="generate wavedrom .wdr.json file",
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action="store_true")
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parser.add_argument(
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"-s",
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"--savesvg",
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help="generate .svg image",
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action="store_true")
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parser.add_argument(
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"-r",
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"--reduceclk",
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help="reduce clock sequences",
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action="store_true")
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parser.add_argument(
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"infile",
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help="VCD waveform file",
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type=pathlib.Path,
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nargs="*")
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args = parser.parse_args()
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if args.all_libs:
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path = pathlib.Path(allcellpath).expanduser()
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parts = path.parts[1:] if path.is_absolute() else path.parts
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paths = pathlib.Path(path.root).glob(str(pathlib.Path("").joinpath(*parts)))
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args.infile = list(paths)
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infile = [d.resolve() for d in args.infile if d.is_file()]
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errors = 0
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for f in infile:
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try:
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wdr = parsetowavedrom(f, args.wavedrom, args.reduceclk)
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if args.savesvg:
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svg = wavedrom.render( quoted_strings_wavedrom(wdr) )
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outfile = f.with_suffix(".svg")
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svg.saveas(outfile)
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except KeyboardInterrupt:
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sys.exit(1)
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except (SyntaxError, AssertionError, FileNotFoundError, ChildProcessError) as ex:
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eprint (f'{type(ex).__name__}: {", ".join(ex.args)}')
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errors +=1
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eprint (f'\n{len(infile)} files processed, {errors} errors.')
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return 0 if errors else 1
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if __name__ == "__main__":
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sys.exit(main())
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@ -0,0 +1,169 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright 2020 The SkyWater PDK Authors.
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#
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# Use of this source code is governed by the Apache 2.0
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# license that can be found in the LICENSE file or at
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# SPDX-License-Identifier: Apache-2.0
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''' This is a cell VCD waveform generation script.
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'''
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import csv
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import json
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import os
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import sys
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import argparse
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import pathlib
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import glob
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import subprocess
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import textwrap
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import re
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def write_vcd (cellpath, define_data, use_power_pins=False):
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''' Generates vcd for a given cell.
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Args:
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cellpath - path to a cell [str of pathlib.Path]
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define_data - cell data from json [dic]
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use_power_pins - include power pins toggling in simulation [bool]
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'''
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# collect power port names
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pp = []
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for p in define_data['ports']:
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if len(p)>2 and p[0]=='power':
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pp.append(p[1])
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# define output file(s)
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ppsuffix = '.pp' if use_power_pins else ''
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outfile = os.path.join(cellpath, define_data['file_prefix'] + ppsuffix + '.vcd')
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vppfile = os.path.join(cellpath, define_data['file_prefix'] + '.vpp.tmp')
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tmptestbed = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v.tmp')
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# find and patch Verilog testbed file
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testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v')
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assert os.path.exists(testbedfile), testbedfile
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insertppdefine = use_power_pins
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insertdumpvars = True
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insertfinish = True
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prvline=''
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with open(tmptestbed,'w') as ttb:
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with open(testbedfile,'r') as tbf:
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for line in tbf:
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# add use_power_pins define
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if insertppdefine and line.startswith('`include'):
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line = '`define USE_POWER_PINS\n' + line
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insertppdefine = False
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# add dumpfile define
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if insertdumpvars and prvline.strip(' \n\r')=='begin':
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line = line[:-len(line.lstrip())] + \
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'$dumpfile("' + outfile + '");\n' + \
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line[:-len(line.lstrip())] + \
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'$dumpvars(1,top);\n' + \
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line
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insertdumpvars = False
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# add finish command, to stop paraller threads
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if insertfinish and line.strip(' \n\r')=='end' and not '$finish' in prvline:
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line = prvline[:-len(prvline.lstrip())] + '$finish;\n' + line
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insertfinish = False
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# remove power pins from reg - optinal, but makes output more readable
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if not use_power_pins:
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for p in pp:
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if re.search( 'reg\s+'+p, line ) is not None or \
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re.search( p+'\s+\=', line ) is not None :
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line=''
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break
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# remove power pins from dut
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if not use_power_pins and define_data['file_prefix']+' dut' in line:
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for p in pp:
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line = line.replace(f'.{p}({p}),','')
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line = line.replace(f'.{p}({p}))',')')
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prvline = line
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ttb.write(line)
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# generate vpp code and vcd recording
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if subprocess.call(['iverilog', '-o', vppfile, tmptestbed], cwd=cellpath):
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raise ChildProcessError("Icarus Verilog compilation failed")
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if subprocess.call(['vvp', vppfile], cwd=cellpath):
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raise ChildProcessError("Icarus Verilog runtime failed")
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# remove temporary files
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os.remove(tmptestbed)
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os.remove(vppfile)
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def process(cellpath):
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''' Processes cell indicated by path.
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Opens cell definiton and calls further processing
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Args:
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cellpath - path to a cell [str of pathlib.Path]
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'''
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print()
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print(cellpath)
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define_json = os.path.join(cellpath, 'definition.json')
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if not os.path.exists(define_json):
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print("No definition.json in", cellpath)
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assert os.path.exists(define_json), define_json
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define_data = json.load(open(define_json))
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if define_data['type'] == 'cell':
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write_vcd(cellpath, define_data, use_power_pins = False)
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write_vcd(cellpath, define_data, use_power_pins = True)
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return
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def main():
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''' Generates VCD waveform for cell.'''
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prereq_txt = ''
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output_txt = 'output:\n generates [fullcellname].vcd'
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allcellpath = '../../../libraries/*/latest/cells/*'
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parser = argparse.ArgumentParser(
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description = main.__doc__,
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epilog = prereq_txt +'\n\n'+ output_txt,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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parser.add_argument(
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"--all_libs",
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help="process all cells in "+allcellpath,
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action="store_true")
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parser.add_argument(
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"cell_dir",
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help="path to the cell directory",
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type=pathlib.Path,
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nargs="*")
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args = parser.parse_args()
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if args.all_libs:
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path = pathlib.Path(allcellpath).expanduser()
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parts = path.parts[1:] if path.is_absolute() else path.parts
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paths = pathlib.Path(path.root).glob(str(pathlib.Path("").joinpath(*parts)))
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args.cell_dir = list(paths)
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cell_dirs = [d.resolve() for d in args.cell_dir if d.is_dir()]
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errors = 0
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for d in cell_dirs:
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try:
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process(d)
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except KeyboardInterrupt:
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sys.exit(1)
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except (AssertionError, FileNotFoundError, ChildProcessError) as ex:
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print (f'Error: {type(ex).__name__}')
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print (f'{ex.args}')
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errors +=1
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print (f'\n{len(cell_dirs)} files processed, {errors} errors.')
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return 0 if errors else 1
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if __name__ == "__main__":
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sys.exit(main())
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