From 33ff0a206547f9e800b782ed0d62190012760c39 Mon Sep 17 00:00:00 2001 From: Kane York Date: Sat, 8 Aug 2020 17:03:39 -0700 Subject: [PATCH 1/3] glossary: Add suggestions from Slack Alphabetize the acronyms section. Fix the link to Mentor Graphics. --- docs/glossary.rst | 93 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 69 insertions(+), 24 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 553fde5..7124162 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -18,10 +18,16 @@ Glossary Mentor Mentor Graphics - `Mentor, a Siemens Business is a US-based electronic design automation (EDA) multinational corporation for electrical engineering and electronics. ` + `Mentor, a Siemens Business `_ + is a US-based electronic design automation (EDA) multinational + corporation for electrical engineering and electronics. OSU Oklahoma State University + + VSD + VLSI System Design + `VLSI System Design `_ .. Acronyms @@ -34,6 +40,15 @@ Glossary ce Memory Core + CIF + Caltech Intermediate Form + From the 1990's, the CIF format has largely been replaced by the GDS + format. + + CCS + ECSM + Current Source Models + DRC Design Rule Check Design Rule Checking @@ -41,35 +56,17 @@ Glossary physical layout of a particular chip layout satisfies a series of required parameters called design rules. + ESD + Electro-Static Discharge (protection from) + Circuit elements, especially on I/O pins, intended to protect the circuit + from the effects of `electrostatic discharge `_. + LVS Layout Verse Schematic Layout Versus Schematic (LVS) verification is the process of determining whether a particular integrated circuit layout corresponds to the original :ref:`schematic` or :ref:`circuit diagram` of the design. - PEX - Parasitic Extraction - Parasitic extraction is calculation of the parasitic effects in both the - designed devices and the required wiring interconnects of an electronic - circuit. This includes all parasitic components (often called parasitic - devices) including parasitic; - - * capacitances, - * resistances, and - * inductances. - - NLDM - Non-Linear Delay Model - - CCS - ECSM - Current Source Models - - - CIF - Caltech Intermediate Form - From the 1990's, the CIF format has largely been replaced by the GDS - format. MiM MIM MiM caps @@ -97,7 +94,48 @@ Glossary The capacitance of MoM caps is capacitance of the metal sidewalls which is significantly lower than that provided MiM caps. + + NLDM + Non-Linear Delay Model + OPHW + OPen HardWare + The movement to produce inspectable and modifiable computer hardware + designs. + + PEX + Parasitic Extraction + Parasitic extraction is calculation of the parasitic effects in both the + designed devices and the required wiring interconnects of an electronic + circuit. This includes all parasitic components (often called parasitic + devices) including parasitic; + + * capacitances, + * resistances, and + * inductances. + + PNR + Place aNd Route + The process of laying out the standard design cells on the 2D plane of the + chip and connecting their corresponding inputs and outputs. Theoretically + equivalent to the "Travelling Salesman Problem," and therefore the subject + of much research. + + STA + Static Timing Analysis + Analysing the timing of a circuit from some level of the design. Contrast + with performing the timing analysis on actual hardware. + + RTL + Register Transfer Language + A source code format that describes the transitions that hardware + registers take at the register transfer level, such as Verilog or VHDL. + + VLSI + Very Large Scale Integration + Producing an integrated circuit in the million+ transistor scale, with + multiple functions on the same chip (such as compute, memory, ROM, and + power regulation). .. File formats @@ -142,6 +180,13 @@ Glossary OpenRoad The digital design flow developed by `The OpenRoad Project `_ + + qflow + `qflow `_ + Named after Steve Beccue of MultiGIG. + + yosys + `Yosys Open SYnthesis Suite `_ .. Terms specific to this documentation From 487438bd69b2bd22aec4e5c6853f5540b1ead179 Mon Sep 17 00:00:00 2001 From: Kane York Date: Sat, 8 Aug 2020 17:19:29 -0700 Subject: [PATCH 2/3] Add brief description of antenna rules, headings attempt to make headings render --- docs/glossary.rst | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 7124162..32d8410 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,6 +4,8 @@ Glossary .. Companies .. glossary:: + Companies + ######### SkyWater SkyWater Technology @@ -32,6 +34,8 @@ Glossary .. Acronyms .. glossary:: + Acronyms + ######### sc Standard Cell @@ -40,6 +44,12 @@ Glossary ce Memory Core + Antenna Rule Violations + During manufacturing, a static charge can build up on the currently- + topmost metal layer, and destroy the chip if there is no path to the + substrate for this charge to bleed off during layer deposition. The + Antenna Rule ensures that each metal layer has a route to diffusion. + CIF Caltech Intermediate Form From the 1990's, the CIF format has largely been replaced by the GDS @@ -47,7 +57,7 @@ Glossary CCS ECSM - Current Source Models + Current Source Models DRC Design Rule Check @@ -141,6 +151,8 @@ Glossary .. File formats .. glossary:: + File formats + ######### .lef LEF @@ -166,6 +178,8 @@ Glossary .. Tools .. glossary:: + Tools + ######### Mentor Calibre The Calibre® product suite developed by :term:`Mentor Graphics`. Heavily From c62246da3b6b5ce9e2257377e3ebaddb33558c87 Mon Sep 17 00:00:00 2001 From: Kane York Date: Sat, 8 Aug 2020 17:24:38 -0700 Subject: [PATCH 3/3] Undo attempt to add headings --- docs/glossary.rst | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 32d8410..49c4bc1 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,9 +4,6 @@ Glossary .. Companies .. glossary:: - Companies - ######### - SkyWater SkyWater Technology `SkyWater Technology `_ @@ -34,9 +31,6 @@ Glossary .. Acronyms .. glossary:: - Acronyms - ######### - sc Standard Cell The basic building blocks of digital circuit design. @@ -151,9 +145,6 @@ Glossary .. File formats .. glossary:: - File formats - ######### - .lef LEF Library Exchange Format @@ -178,9 +169,6 @@ Glossary .. Tools .. glossary:: - Tools - ######### - Mentor Calibre The Calibre® product suite developed by :term:`Mentor Graphics`. Heavily used for IC Verification and Signoff.