Apply changes to generated CSV and RST files

docs/rules/periphery-rules.rst

@@ -1,7 +1,7 @@
 .. Do **not** modify this file it is generated from the periphery.csv file
    found in the periphery directory using the
-   ./periphery/periphery-split-csv.py script.
-.. Instead run `make rules/periphery-rules.rst` in the ./docs directory.
+   ./periphery/periphery-split-csv.py script. Instead run `make
+   rules/periphery-rules.rst` in the ./docs directory.
 
 .. list-table::
    :header-rows: 1
@@ -321,7 +321,7 @@
      - 
 
 
-.. figure:: periphery/p018-x_dotdash.svg
+.. figure:: periphery\p018-x_dotdash.svg
     :width: 100%
     :align: center
 
@@ -376,9 +376,13 @@
      - RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs)
      - 
      - 
+   * - :drc_rule:`(dnwell.7)`
+     - Dnwell can not straddle areaid:substratecut
+     - 
+     - 
 
 
-.. figure:: periphery/p020-dnwell_dotdash.svg
+.. figure:: periphery\p020-dnwell_dotdash.svg
     :width: 100%
     :align: center
 
@@ -433,11 +437,12 @@
    * - :drc_rule:`(nwell.7)`
      - Min spacing between nwell and deep nwell on separate nets
         Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the "joinNets" switch should be turned on.
+        waffle_chip
      - :drc_flag:`TC`
      - 4.500
 
 
-.. figure:: periphery/p021-nwell_dotdash.svg
+.. figure:: periphery\p021-nwell_dotdash.svg
     :width: 100%
     :align: center
 
@@ -472,9 +477,13 @@
      - dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell)
      - 
      - N/A
+   * - :drc_rule:`(pwbm.5)`
+     - Min Space between two pwbm holes inside UHVI
+     - 
+     - N/A
 
 
-.. figure:: periphery/p022-pwbm_dotdash.svg
+.. figure:: periphery\p022-pwbm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -513,9 +522,13 @@
      - pwdem.dg inside UHVI must be enclosed by deep nwell
      - 
      - N/A
+   * - :drc_rule:`(pwdem.6)`
+     - Min enclosure of pwdem:dg by deep nwell inside UHVI
+     - 
+     - N/A
 
 
-.. figure:: periphery/p022-pwdem_dotdash.svg
+.. figure:: periphery\p022-pwdem_dotdash.svg
     :width: 100%
     :align: center
 
@@ -554,9 +567,13 @@
      - Min area of hvtp (um^2)
      - 
      - 0.265
+   * - :drc_rule:`(hvtp.6)`
+     - Min area of hvtp Holes (um^2)
+     - 
+     - 0.265
 
 
-.. figure:: periphery/p023-hvtp_dotdash.svg
+.. figure:: periphery\p023-hvtp_dotdash.svg
     :width: 100%
     :align: center
 
@@ -583,6 +600,10 @@
      - Min spacing between hvtp to hvtr
      - 
      - 0.380
+   * - :drc_rule:`(hvtr.3)`
+     - Min enclosure of pfet by hvtr
+     - :drc_flag:`P`
+     - 0.180
 
 
 
@@ -635,9 +656,13 @@
      - Min area of lvtn (um^2)
      - 
      - 0.265
+   * - :drc_rule:`(lvtn.14)`
+     - Min area of lvtn Holes (um^2)
+     - 
+     - 0.265
 
 
-.. figure:: periphery/p024-lvtn_dotdash.svg
+.. figure:: periphery\p024-lvtn_dotdash.svg
     :width: 100%
     :align: center
 
@@ -696,9 +721,13 @@
      - Min area of ncm (um^2)
      - 
      - 0.265
+   * - :drc_rule:`(ncm.8)`
+     - Min area of ncm Holes (um^2)
+     - 
+     - 0.265
 
 
-.. figure:: periphery/p025-ncm_dotdash.svg
+.. figure:: periphery\p025-ncm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -773,9 +802,13 @@
      - ESD_nwell_tap is considered shorted to the abutting diff
      - :drc_flag:`NC`
      - 
+   * - :drc_rule:`(difftap.13)`
+     - Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.
+     - 
+     - 
 
 
-.. figure:: periphery/p026-difftap_dotdash.svg
+.. figure:: periphery\p026-difftap_dotdash.svg
     :width: 100%
     :align: center
 
@@ -822,9 +855,13 @@
      - Min tunm area
      - 
      - 0.672
+   * - :drc_rule:`(tunm.8)`
+     - tunm must be enclosed by :drc_tag:`areaid.ce`
+     - 
+     - 
 
 
-.. figure:: periphery/p027-tunm_dotdash.svg
+.. figure:: periphery\p027-tunm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -907,9 +944,13 @@
      - Poly must not overlap diff:rs
      - 
      - 
+   * - :drc_rule:`(poly.16)`
+     - Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances
+     - 
+     - 
 
 
-.. figure:: periphery/p028-poly_dotdash.svg
+.. figure:: periphery\p028-poly_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1008,9 +1049,13 @@
      - Min spacing of rpm to pwbm
      - 
      - N/A
+   * - :drc_rule:`(rpm.11)`
+     - rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp
+     - 
+     - N/A
 
 
-.. figure:: periphery/p029-rpm_dotdash.svg
+.. figure:: periphery\p029-rpm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1057,9 +1102,13 @@
      - Nwell overlapping Var_channel must not overlap P+ diff
      - 
      - 
+   * - :drc_rule:`(varac.8)`
+     - Min enclosure of Var_channel by hvtp
+     - 
+     - 0.255
 
 
-.. figure:: periphery/p030-varac_dotdash.svg
+.. figure:: periphery\p030-varac_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1118,9 +1167,13 @@
      - Min/Max width of tap inside photoDiode
      - 
      - 0.410
+   * - :drc_rule:`(photo.11)`
+     - Min/Max enclosure of tap by nwell inside photoDiode
+     - 
+     - 0.215
 
 
-.. figure:: periphery/p031-photo_dotdash.svg
+.. figure:: periphery\p031-photo_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1155,9 +1208,13 @@
      - Spacing (no overlap) of NPC to Gate
      - 
      - 0.090
+   * - :drc_rule:`(npc.5)`
+     - Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min)
+     - 
+     - 0.095
 
 
-.. figure:: periphery/p032-npc_dotdash.svg
+.. figure:: periphery\p032-npc_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1220,9 +1277,13 @@
      - Min area of Psdm (um^2)
      - 
      - 0.255
+   * - :drc_rule:`(n/ psd.11)`
+     - Min area of n/psdmHoles (um^2)
+     - 
+     - 0.265
 
 
-.. figure:: periphery/p032-n_psd_dotdash.svg
+.. figure:: periphery\p032-n_psd_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1361,9 +1422,13 @@
      - Npc must enclose poly_licon
      - 
      - 
+   * - :drc_rule:`(licon.19)`
+     - poly of the HV varactor must not interact with licon
+     - :drc_flag:`P`
+     - 
 
 
-.. figure:: periphery/p034-licon_dotdash.svg
+.. figure:: periphery\p034-licon_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1410,9 +1475,13 @@
      - Min area of LI
      - :drc_flag:`P`
      - 0.0561
+   * - :drc_rule:`(li.7.-)`
+     - Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)
+     - 
+     - 0.290
 
 
-.. figure:: periphery/p035-li_dotdash_dotdash.svg
+.. figure:: periphery\p035-li_dotdash_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1455,9 +1524,13 @@
      - For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.3
+   * - :drc_rule:`(ct.irdrop.3)`
+     - For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.7
 
 
-.. figure:: periphery/p035-ct_dotdash.svg
+.. figure:: periphery\p035-ct_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1520,9 +1593,13 @@
      - Min spacing between capm to (met2 not overlapping capm)
      - 
      - N/A
+   * - :drc_rule:`(capm.12)`
+     - Max area of capm (um^2)
+     - 
+     - N/A
 
 
-.. figure:: periphery/p036-capm_dotdash.svg
+.. figure:: periphery\p036-capm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1609,9 +1686,13 @@
      - Min space of met1 to met1inside VPP capacitor
      - :drc_flag:`CU`
      - 0.160
+   * - :drc_rule:`(vpp.14)`
+     - Min space of met2 to met2 inside VPP capacitor
+     - :drc_flag:`CU`
+     - 0.160
 
 
-.. figure:: periphery/p037-vpp_dotdash.svg
+.. figure:: periphery\p037-vpp_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1702,9 +1783,13 @@
      - Met1 PD window step
      - :drc_flag:`CU`
      - 25.000
+   * - :drc_rule:`(m1.15)`
+     - Mcon must be enclosed by met1 on one of two adjacent sides by at least …
+     - :drc_flag:`CU`
+     - 0.030
 
 
-.. figure:: periphery/p038-m1_dotdash.svg
+.. figure:: periphery\p038-m1_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1795,9 +1880,13 @@
      - For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.9
+   * - :drc_rule:`(via.14a)`
+     - 0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …
+     - :drc_flag:`CU`
+     - 0.037
 
 
-.. figure:: periphery/p039-via_dotdash.svg
+.. figure:: periphery\p039-via_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1888,9 +1977,13 @@
      - Met2 PD window step
      - :drc_flag:`CU`
      - 25.000
+   * - :drc_rule:`(m2.15)`
+     - Via must be enclosed by met2 by at least…
+     - :drc_flag:`CU`
+     - 0.040
 
 
-.. figure:: periphery/p040-m2_dotdash.svg
+.. figure:: periphery\p040-m2_dotdash.svg
     :width: 100%
     :align: center
 
@@ -1985,9 +2078,13 @@
      - For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.79
+   * - :drc_rule:`(via2.irdrop.4)`
+     - For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.9
 
 
-.. figure:: periphery/p041-via2_dotdash.svg
+.. figure:: periphery\p041-via2_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2086,9 +2183,13 @@
      - Met3 PD window step
      - :drc_flag:`CU`
      - 25.000
+   * - :drc_rule:`(m3.15)`
+     - Via2 must be enclosed by met3 by at least…
+     - :drc_flag:`CU`
+     - 0.060
 
 
-.. figure:: periphery/p042-m3_dotdash.svg
+.. figure:: periphery\p042-m3_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2159,6 +2260,10 @@
      - For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.8
+   * - :drc_rule:`(via3.irdrop.4)`
+     - For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.9
 
 
 
@@ -2191,6 +2296,10 @@
      - Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name "s8Fab_crntic*"  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
      - 
      - 3.000
+   * - :drc_rule:`(nsm.3b)`
+     - Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
+     - 
+     - 3.000
 
 
 
@@ -2219,9 +2328,13 @@
      - top_padVia must  be enclosed by top_indmMetal by atleast
      - 
      - N/A
+   * - :drc_rule:`(indm.4)`
+     - Min area of top_indmMetal
+     - 
+     - N/A
 
 
-.. figure:: periphery/p043-indm_dotdash.svg
+.. figure:: periphery\p043-indm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2312,9 +2425,13 @@
      - Via3 must be enclosed by met4 by at least…
      - :drc_flag:`CU`
      - 0.060
+   * - :drc_rule:`(m4.16)`
+     - Min enclosure of pad by met4
+     - :drc_flag:`CU`
+     - 0.850
 
 
-.. figure:: periphery/p044-m4_dotdash.svg
+.. figure:: periphery\p044-m4_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2361,6 +2478,10 @@
      - For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
      - :drc_flag:`CU` :drc_flag:`IR`
      - 0.5
+   * - :drc_rule:`(via4.irdrop.4)`
+     - For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…
+     - :drc_flag:`CU` :drc_flag:`IR`
+     - 0.8
 
 
 
@@ -2389,6 +2510,10 @@
      - via4 must  be enclosed by met5 by atleast
      - 
      - 0.310
+   * - :drc_rule:`(m5.4)`
+     - Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)
+     - 
+     - 4.000
 
 
 
@@ -2409,6 +2534,10 @@
      - Min spacing of pad:dg to pad:dg
      - 
      - 1.270
+   * - :drc_rule:`(pad.3)`
+     - Max area of hugePad NOT top_metal
+     - 
+     - 30000
 
 
 
@@ -2445,6 +2574,10 @@
      - (rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)
      - 
      - 
+   * - :drc_rule:`(rdl.6)`
+     - Min spacing of rdl to pad, except rdl interacting with bump
+     - 
+     - 19.660
 
 
 
@@ -2564,9 +2697,13 @@
      - Spacing (no overlapping) between fuse center and Metal5
      - 
      - 3.300
+   * - :drc_rule:`(mf.Section G2b: Rules for HV devices)`
+     - 
+     - 
+     - 
 
 
-.. figure:: periphery/p046-mf_dotdash.svg
+.. figure:: periphery\p046-mf_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2601,9 +2738,13 @@
      - Hvi must not overlap tunm
      - 
      - 
+   * - :drc_rule:`(hvi.5)`
+     - Min space between hvi and nwell (exclude coincident edges)
+     - 
+     - 0.700
 
 
-.. figure:: periphery/p047-hvi_dotdash.svg
+.. figure:: periphery\p047-hvi_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2612,11 +2753,7 @@
 :drc_rule:`(hvnwell.-)`
 -----------------------
 
-* All nwell connected to voltages greater than 1.8V must be enclosed by hvi
-* Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged "lv_net" using text.dg
-* This tag should be only on Li layer
-
-.. list-table:: Function: Defines rules for HV nwell.
+.. list-table:: Function: Defines rules for HV nwell; All nwell connected to voltages greater than 1.8V must be enclosed by hvi; Nets connected to LV nwell or nwell overlapping hvi but connected to LV voltages (i.e 1.8V) should be tagged "lv_net" using text.dg; This tag should be only on Li layer
    :header-rows: 1
    :stub-columns: 1
    :width: 100%
@@ -2638,9 +2775,13 @@
      - LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged "lv_net" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`
      - :drc_flag:`TC`
      - 
+   * - :drc_rule:`(hvnwell.11)`
+     - Nwell connected to the nets mentioned in the "Power_Net_Hv" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells "s8tsg5_tx_ibias_gen" and "s8bbcnv_psoc3p_top_18",  "rainier_top, indus_top*", "rainier_top, manas_top, ccg3_top"
+     - 
+     - 
 
 
-.. figure:: periphery/p047-hvnwell_dotdash.svg
+.. figure:: periphery\p047-hvnwell_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2715,9 +2856,13 @@
      - Min space of N+ Hdiff inside HVI across non-abutting P+_tap
      - :drc_flag:`NC`
      - 1.070
+   * - :drc_rule:`(hvdifftap.26)`
+     - Min spacing between pwbm to difftap outside UHVI
+     - 
+     - N/A
 
 
-.. figure:: periphery/p048-hvdifftap_dotdash.svg
+.. figure:: periphery\p048-hvdifftap_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2740,9 +2885,13 @@
      - Min width of poly over diff inside Hvi
      - :drc_flag:`P`
      - 0.500
+   * - :drc_rule:`(hvpoly.14)`
+     - (poly and diff) cannot straddle Hvi
+     - 
+     - 
 
 
-.. figure:: periphery/p049-hvpoly_dotdash.svg
+.. figure:: periphery\p049-hvpoly_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2801,9 +2950,13 @@
      - Hvntm must not overlap :drc_tag:`areaid.ce`
      - 
      - 
+   * - :drc_rule:`(hvntm.10)`
+     - Hvntm must overlap hvi
+     - 
+     - 
 
 
-.. figure:: periphery/p049-hvntm_dotdash.svg
+.. figure:: periphery\p049-hvntm_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2878,9 +3031,13 @@
      - de_nFet_source must be enclosed by nsdm by
      - 
      - 0.130
+   * - :drc_rule:`(denmos.14)`
+     - nvhv FETs must be enclosed by :drc_tag:`areaid.mt`
+     - 
+     - N/A
 
 
-.. figure:: periphery/p050-denmos_dotdash.svg
+.. figure:: periphery\p050-denmos_dotdash.svg
     :width: 100%
     :align: center
 
@@ -2951,9 +3108,13 @@
      - de_pFet_source must be enclosed by psdm by
      - 
      - 0.130
+   * - :drc_rule:`(depmos.13)`
+     - pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`
+     - 
+     - N/A
 
 
-.. figure:: periphery/p051-depmos_dotdash.svg
+.. figure:: periphery\p051-depmos_dotdash.svg
     :width: 100%
     :align: center
 
@@ -3000,9 +3161,13 @@
      - Only cell name "s8rf_n20nativevhv1*" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)
      - 
      - N/A
+   * - :drc_rule:`(extd.8)`
+     - Only cell name "s8rf_n20zvtvhv1*" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)
+     - 
+     - N/A
 
 
-.. figure:: periphery/p052-extd_dotdash.svg
+.. figure:: periphery\p052-extd_dotdash.svg
     :width: 100%
     :align: center
 
@@ -3098,9 +3263,13 @@
      - Minimum overlap of hv poly ring_FET and diff
      - 
      - 
+   * - :drc_rule:`(hv.poly.8)`
+     - Any poly gate abutting hv_source/drain becomes a hvFET_gate
+     - 
+     - 
 
 
-.. figure:: periphery/p054-hv_dotdash_dotdash.svg
+.. figure:: periphery\p054-hv_dotdash_dotdash.svg
     :width: 100%
     :align: center
 
@@ -3171,6 +3340,10 @@
      - Vhvi:dg cannot straddle VHVPoly
      - 
      - 
+   * - :drc_rule:`(vhvi.8.-)`
+     - Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).
+     - 
+     - 11.240
 
 
 
@@ -3223,6 +3396,10 @@
      - Minimum Space spacing of natfet.dg
      - 
      - N/A
+   * - :drc_rule:`(uhvi.10.-)`
+     - natfet.dg layer is not allowed
+     - 
+     - N/A
 
 
 
@@ -3247,6 +3424,10 @@
      - :drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted "condiodeHvPsub"
      - 
      - NA
+   * - :drc_rule:`(ulvt-.3)`
+     - :drc_tag:`areaid.low_vt` can not straddle UHVI
+     - 
+     - NA
 
 
 
@@ -3307,9 +3488,13 @@
      - The res layer must abut pwres_terminal on opposite and parallel edges
      - 
      - 
+   * - :drc_rule:`(pwres.11.-)`
+     - The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10
+     - 
+     - 
 
 
-.. figure:: periphery/p056-pwres_dotdash_dotdash.svg
+.. figure:: periphery\p056-pwres_dotdash_dotdash.svg
     :width: 100%
     :align: center
 
@@ -3341,11 +3526,12 @@
         Allowed PNP layout
         Layout: pnppar
         Allowed NPN layout
+        Layout: npnpar1x1
      - 
      - 
 
 
-.. figure:: periphery/p057-rfdiode_dotdash_dotdash.svg
+.. figure:: periphery\p057-rfdiode_dotdash_dotdash.svg
     :width: 100%
     :align: center
 

docs/rules/periphery/p020-dnwell_dotdash.csv

@@ -8,3 +8,4 @@ Name,Description,Flags,Value
 (dnwell.4),Dnwell can not overlap pnp:dg,,
 (dnwell.5),P+_diff can not straddle Dnwell,,
 (dnwell.6),RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs),,
+(dnwell.7),Dnwell can not straddle areaid:substratecut,,

docs/rules/periphery/p021-nwell_dotdash.csv

@@ -9,4 +9,5 @@ Nwells can merge over deep nwell if spacing too small (as in rule nwell.2)",TC,0
 (nwell.5b),nwell inside UHVI must not be on the same net as nwell outside UHVI,,N/A
 (nwell.6),Min enclosure of nwell hole by deep nwell outside UHVI,TC,1.030
 (nwell.7),"Min spacing between nwell and deep nwell on separate nets
-Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.",TC,4.500
+Spacing between nwell and deep nwell on the same net is set by the sum of the rules nwell.2 and nwell.5. By default, DRC run on a cell checks for the separate-net spacing, when nwell and deep nwell nets are separate within the cell hierarchy and are joined in the upper hierarchy. To allow net names to be joined and make the same-net rule applicable in this case, the ""joinNets"" switch should be turned on.
+waffle_chip",TC,4.500

docs/rules/periphery/p022-pwbm_dotdash.csv

@@ -3,3 +3,4 @@ Name,Description,Flags,Value
 (pwbm.2),Min spacing between two pwbm.dg inside UHVI,,N/A
 (pwbm.3),Min enclosure of dnwell:dg by pwbm.dg inside UHVI (exempt pwbm hole inside dnwell),,N/A
 (pwbm.4),dnwell inside UHVI must be enclosed by pwbm (exempt pwbm hole inside dnwell),,N/A
+(pwbm.5),Min Space between two pwbm holes inside UHVI,,N/A

docs/rules/periphery/p022-pwdem_dotdash.csv

@@ -4,3 +4,4 @@ Name,Description,Flags,Value
 (pwdem.3),Min enclosure of pwdem:dg by pwbm.dg inside UHVI,,N/A
 (pwdem.4),pwdem.dg must be enclosed by UHVI,,N/A
 (pwdem.5),pwdem.dg inside UHVI must be enclosed by deep nwell,,N/A
+(pwdem.6),Min enclosure of pwdem:dg by deep nwell inside UHVI,,N/A

docs/rules/periphery/p023-hvtp_dotdash.csv

@@ -4,3 +4,4 @@ Name,Description,Flags,Value
 (hvtp.3),Min enclosure of pfet by hvtp,P,0.180
 (hvtp.4),Min spacing between pfet and hvtp,P,0.180
 (hvtp.5),Min area of hvtp (um^2),,0.265
+(hvtp.6),Min area of hvtp Holes (um^2),,0.265

docs/rules/periphery/p024-hvtr_dotdash.csv

@@ -1,3 +1,4 @@
 Name,Description,Flags,Value
 (hvtr.1),Min width of hvtr,,0.380
 (hvtr.2),Min spacing between hvtp to hvtr,,0.380
+(hvtr.3),Min enclosure of pfet by hvtr,P,0.180

docs/rules/periphery/p024-lvtn_dotdash.csv

@@ -8,3 +8,4 @@ Name,Description,Flags,Value
 (lvtn.10),Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges),,0.380
 (lvtn.12),Min spacing between lvtn and (nwell inside :drc_tag:`areaid.ce`),,0.380
 (lvtn.13),Min area of lvtn (um^2),,0.265
+(lvtn.14),Min area of lvtn Holes (um^2),,0.265

docs/rules/periphery/p025-ncm_dotdash.csv

@@ -9,3 +9,4 @@ Name,Description,Flags,Value
 (ncm.5),"Min space, no overlap, between ncm and (LVTN_gate) OR (diff containing lvtn)",P,0.230
 (ncm.6),"Min space, no overlap, between ncm and nfet",P,0.200
 (ncm.7),Min area of ncm (um^2),,0.265
+(ncm.8),Min area of ncm Holes (um^2),,0.265

docs/rules/periphery/p026-difftap_dotdash.csv

@@ -13,3 +13,4 @@ Name,Description,Flags,Value
 (difftap.10),Enclosure of (n+)  tap by N-well. Rule exempted inside UHVI.,NE P,0.180
 (difftap.11),Spacing of (p+) tap to  N-well. Rule exempted inside UHVI.,,0.130
 (difftap.12),ESD_nwell_tap is considered shorted to the abutting diff,NC,
+(difftap.13),Diffusion or the RF FETS in Table H5 is defined by Ldiff and Wdiff.,,

docs/rules/periphery/p027-tunm_dotdash.csv

@@ -6,3 +6,4 @@ Name,Description,Flags,Value
 (tunm.5),(poly and diff) may not straddle tunm,,
 (tunm.6a),Tunm outside deep n-well is not allowed,TC,
 (tunm.7),Min tunm area,,0.672
+(tunm.8),tunm must be enclosed by :drc_tag:`areaid.ce`,,

docs/rules/periphery/p028-poly_dotdash.csv

@@ -15,3 +15,4 @@ Name,Description,Flags,Value
 (poly.11),No 90 deg turns of poly on diff,,
 (poly.12),"(Poly NOT (nwell NOT hvi)) may not overlap tap; Rule exempted for cell name ""s8fgvr_n_fg2"" and gated_npn and inside UHVI.",P,
 (poly.15),Poly must not overlap diff:rs,,
+(poly.16),"Inside RF FETs defined in Table H5, poly cannot overlap poly across multiple adjacent instances",,

docs/rules/periphery/p029-rpm_dotdash.csv

@@ -19,3 +19,4 @@ Name,Description,Flags,Value
 (rpm.8),poly must not straddle rpm,,
 (rpm.9),"Min space, no overlap, between prec_resistor and hvntm",,0.185
 (rpm.10),Min spacing of rpm to pwbm,,N/A
+(rpm.11),rpm should not overlap or straddle pwbm except cells\ns8usbpdv2_csa_top\ns8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit\ns8usbpdv2_20vconn_sw_300ma_ovp\ns8usbpdv2_20sbu_sw_300ma_ovp,,N/A

docs/rules/periphery/p030-varac_dotdash.csv

@@ -6,3 +6,4 @@ Name,Description,Flags,Value
 (varac.5),Min enclosure of poly overlapping Var_channel by nwell,,0.150
 (varac.6),Min spacing between VaracTap and difftap,,0.270
 (varac.7),Nwell overlapping Var_channel must not overlap P+ diff,,
+(varac.8),Min enclosure of Var_channel by hvtp,,0.255

docs/rules/periphery/p031-photo_dotdash.csv

@@ -9,3 +9,4 @@ Name,Description,Flags,Value
 (photo.8),Min/Max width of nwell inside photoDiode,,0.840
 (photo.9),Min/Max enclosure of nwell by photoDiode,,1.080
 (photo.10),Min/Max width of tap inside photoDiode,,0.410
+(photo.11),Min/Max enclosure of tap by nwell inside photoDiode,,0.215

docs/rules/periphery/p032-n_psd_dotdash.csv

@@ -10,3 +10,4 @@ Name,Description,Flags,Value
 (n/ psd.9),"Diff and tap must be enclosed by their corresponding implant layers. Rule exempted for\n- diff inside ""advSeal_6um* OR cuPillarAdvSeal_6um*"" pcell for SKY130P*/SP8P*/SKY130DI-5R-CSMC flows\n- diff rings around the die at min total L>1000 um and W=0.3 um\n- gated_npn \n- :drc_tag:`areaid.zer`.",DE,
 (n/ psd.10a),Min area of Nsdm (um^2),,0.265
 (n/ psd.10b),Min area of Psdm (um^2),,0.255
+(n/ psd.11),Min area of n/psdmHoles (um^2),,0.265

docs/rules/periphery/p032-npc_dotdash.csv

@@ -3,3 +3,4 @@ Name,Description,Flags,Value
 (npc.2),Min spacing of NPC to NPC,,0.270
 (npc.3),Manual merge if less than minimum,,
 (npc.4),Spacing (no overlap) of NPC to Gate,,0.090
+(npc.5),Max enclosure of poly overlapping slotted_licon by npcm (merge between adjacent short edges of the slotted_licons if space < min),,0.095

docs/rules/periphery/p034-licon_dotdash.csv

@@ -29,3 +29,4 @@ Name,Description,Flags,Value
 (licon.16),"Every source_diff and every tap must enclose at least one licon1, including the diff/tap straddling areaid:ce. \nRule exempted inside UHVI.",P,
 (licon.17),Licons may not overlap both poly and (diff or tap),,
 (licon.18),Npc must enclose poly_licon,,
+(licon.19),poly of the HV varactor must not interact with licon,P,

docs/rules/periphery/p035-ct_dotdash.csv

@@ -5,3 +5,4 @@ Name,Description,Flags,Value
 (ct.4),Mcon must be enclosed by LI by at least …,P,0.000
 (ct.irdrop.1),"For 1 <= n <= 10 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
 (ct.irdrop.2),"For 11 <= n <= 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.3
+(ct.irdrop.3),"For n > 100 contacts on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.7

docs/rules/periphery/p035-li_dotdash_dotdash.csv

@@ -6,3 +6,4 @@ Name,Description,Flags,Value
 (li.3a.-),Spacing of LI to LI inside cells with names s8rf2_xcmvpp_hd5_*,P,0.140
 (li.5.-),Enclosure of licon by one of two adjacent LI sides,P,0.080
 (li.6.-),Min area of LI,P,0.0561
+(li.7.-),"Min LI resistor width (rule exempted within :drc_tag:`areaid.ed`; Inside :drc_tag:`areaid.ed`, min width of the li resistor is determined by rule li.1)",,0.290

docs/rules/periphery/p036-capm_dotdash.csv

@@ -10,3 +10,4 @@ Name,Description,Flags,Value
 (capm.8),"Min space, no overlap, between via and capm",,N/A
 (capm.10),"capm must not straddle nwell, diff, tap, poly, li1 and met1 (Rule exempted for capm overlapping capm_2t.dg)",TC,N/A
 (capm.11),Min spacing between capm to (met2 not overlapping capm),,N/A
+(capm.12),Max area of capm (um^2),,N/A

docs/rules/periphery/p037-vpp_dotdash.csv

@@ -16,3 +16,4 @@ Name,Description,Flags,Value
 (vpp.12b),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp11p5x11p7_m3_lim5shield""  must overlap with size 2.01 x 2.01 (no other met4 shapes allowed)",,16.00
 (vpp.12c),"Number of met4 shapes inside capacitor.dg of cell ""s8rf2_xcmvpp4p4x4p6_m3_lim5shield""  must overlap with size 1.5 x 1.5 (no other met4 shapes allowed)",,4.00
 (vpp.13),Min space of met1 to met1inside VPP capacitor,CU,0.160
+(vpp.14),Min space of met2 to met2 inside VPP capacitor,CU,0.160

docs/rules/periphery/p038-m1_dotdash.csv

@@ -17,3 +17,4 @@ Name,Description,Flags,Value
 (m1.13),Max pattern density (PD) of met1,CU,0.77
 (m1.14),Met1 PD window size,CU,50.000
 (m1.14a),Met1 PD window step,CU,25.000
+(m1.15),Mcon must be enclosed by met1 on one of two adjacent sides by at least …,CU,0.030

docs/rules/periphery/p039-via_dotdash.csv

@@ -17,3 +17,4 @@ Name,Description,Flags,Value
 (via.irdrop.2),"For 3 <= n <= 15 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
 (via.irdrop.3),"For 16 <= n <= 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
 (via.irdrop.4),"For n > 30 vias on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9
+(via.14a),0.180 um Via must be enclosed by 45 deg edges of Met1 by at least …,CU,0.037

docs/rules/periphery/p040-m2_dotdash.csv

@@ -17,3 +17,4 @@ Name,Description,Flags,Value
 (m2.13),Max pattern density (PD) of metal2,CU,0.77
 (m2.14),Met2 PD window size,CU,50.000
 (m2.14a),Met2 PD window step,CU,25.000
+(m2.15),Via must be enclosed by met2 by at least…,CU,0.040

docs/rules/periphery/p041-via2_dotdash.csv

@@ -18,3 +18,4 @@ Name,Description,Flags,Value
 (via2.irdrop.1),"For 1 <= n <= 2 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
 (via2.irdrop.2),"For 3 <= n <= 4 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
 (via2.irdrop.3),"For 5 <= n <= 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.79
+(via2.irdrop.4),"For n > 30 via2's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9

docs/rules/periphery/p042-m3_dotdash.csv

@@ -19,3 +19,4 @@ Name,Description,Flags,Value
 (m3.13),Max pattern density (PD) of metal3,CU,0.77
 (m3.14),Met3 PD window size,CU,50.000
 (m3.14a),Met3 PD window step,CU,25.000
+(m3.15),Via2 must be enclosed by met3 by at least…,CU,0.060

docs/rules/periphery/p042-via3_dotdash.csv

@@ -12,3 +12,4 @@ Name,Description,Flags,Value
 (via3.irdrop.1),"For 1 <= n <= 2 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
 (via3.irdrop.2),"For 3 <= n <= 15 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.6
 (via3.irdrop.3),"For 16 <= n <= 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8
+(via3.irdrop.4),"For n > 30 via3's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.9

docs/rules/periphery/p043-indm_dotdash.csv

@@ -2,3 +2,4 @@ Name,Description,Flags,Value
 (indm.1),Min width of top_indmMetal,,N/A
 (indm.2),Min spacing between two top_indmMetal,,N/A
 (indm.3),top_padVia must  be enclosed by top_indmMetal by atleast,,N/A
+(indm.4),Min area of top_indmMetal,,N/A

docs/rules/periphery/p043-nsm_dotdash.csv

@@ -3,3 +3,4 @@ Name,Description,Flags,Value
 (nsm.2),Min. spacing of nsm to nsm,,4.000
 (nsm.3),"Min spacing, no overlap, between NSM_keepout to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) cell name ""nikon*"" and (b) diff ring inside :drc_tag:`areaid.sl`",AL,1.000
 (nsm.3a),"Min enclosure of diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5) by :drc_tag:`areaid.ft`. Exempt the following from the check: (a) cell name ""s8Fab_crntic*""  (b)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000
+(nsm.3b),"Min spacing between :drc_tag:`areaid.dt` to diff.dg, tap.dg, fom.dy, cfom.dg, cfom.mk, poly.dg, p1m.mk, li1.dg, cli1m.mk, metX.dg (X=1 to 5) and cmmX.mk (X=1 to 5). Exempt the following from the check: (a) blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption)",,3.000

docs/rules/periphery/p044-m4_dotdash.csv

@@ -17,3 +17,4 @@ Name,Description,Flags,Value
 (m4.14),Met4 PD window size,CU,50.000
 (m4.14a),Met4 PD window step,CU,25.000
 (m4.15),Via3 must be enclosed by met4 by at least…,CU,0.060
+(m4.16),Min enclosure of pad by met4,CU,0.850

docs/rules/periphery/p044-m5_dotdash.csv

@@ -2,3 +2,4 @@ Name,Description,Flags,Value
 (m5.1),Min width of met5,,1.600
 (m5.2),Min spacing between two met5,,1.600
 (m5.3),via4 must  be enclosed by met5 by atleast,,0.310
+(m5.4),"Min area of met5 (For all flows except SKY130PIR*/SKY130PF*, the rule is exempted for probe pads which are exactly 1.42um by 1.42um)",,4.000

docs/rules/periphery/p044-via4_dotdash.csv

@@ -6,3 +6,4 @@ Name,Description,Flags,Value
 (via4.irdrop.1),"For 1 <= n <= 4 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.0
 (via4.irdrop.2),"For 5 <= n <= 10 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.2
 (via4.irdrop.3),"For 11 <= n <= 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.5
+(via4.irdrop.4),"For n > 100 via4's on the same connector, mcon area pre- and post- Cu conversion must differ by no more than…",CU IR,0.8

docs/rules/periphery/p045-pad_dotdash.csv

@@ -1,2 +1,3 @@
 Name,Description,Flags,Value
 (pad.2),Min spacing of pad:dg to pad:dg,,1.270
+(pad.3),Max area of hugePad NOT top_metal,,30000

docs/rules/periphery/p045-rdl_dotdash.csv

@@ -4,3 +4,4 @@ Name,Description,Flags,Value
 (rdl.3),"Min enclosure of pad by rdl, except rdl interacting with bump",,10.750
 (rdl.4),Min spacing between rdl and outer edge of the seal ring,,15.000
 (rdl.5),(rdl OR ccu1m.mk) must not overlap :drc_tag:`areaid.ft`. Exempt the following from the check: (a)  blankings in the frame (rule uses :drc_tag:`areaid.dt` for exemption),,
+(rdl.6),"Min spacing of rdl to pad, except rdl interacting with bump",,19.660

docs/rules/periphery/p046-mf_dotdash.csv

@@ -23,3 +23,4 @@ Name,Description,Flags,Value
 (mf.22),Min spacing between fuse_contact to fuse_contact,,1.960
 (mf.23),Spacing (no overlapping) between fuse center and Metal4,,N/A
 (mf.24),Spacing (no overlapping) between fuse center and Metal5,,3.300
+(mf.Section G2b: Rules for HV devices),,,

docs/rules/periphery/p047-hvi_dotdash.csv

@@ -3,3 +3,4 @@ Name,Description,Flags,Value
 (hvi.2a),Min spacing of Hvi to Hvi,P,0.700
 (hvi.2b),Manual merge if space is below minimum,,
 (hvi.4),Hvi must not overlap tunm,,
+(hvi.5),Min space between hvi and nwell (exclude coincident edges),,0.700

docs/rules/periphery/p047-hvnwell_dotdash.csv

@@ -2,3 +2,4 @@ Name,Description,Flags,Value
 (hvnwell.8),Min space between HV_nwell  and any nwell on different nets,,2.000
 (hvnwell.9),(Nwell overlapping hvi) must be enclosed by hvi,,
 (hvnwell.10),"LVnwell and HnWell should not be on the same net (for the purposes of this check, short the connectivity through resistors); Exempt HnWell with li nets tagged ""lv_net"" using text.dg and Hnwell connected to nwell overlapping :drc_tag:`areaid.hl`",TC,
+(hvnwell.11),"Nwell connected to the nets mentioned in the ""Power_Net_Hv"" field of the latcup GUI must be enclosed by hvi (exempt nwell inside :drc_tag:`areaid.hl`). Also for the purposes of this check, short the connectivity through resistors. The rule will be checked in the latchup run and exempted for cells ""s8tsg5_tx_ibias_gen"" and ""s8bbcnv_psoc3p_top_18"",  ""rainier_top, indus_top*"", ""rainier_top, manas_top, ccg3_top""",,

docs/rules/periphery/p048-hvdifftap_dotdash.csv

@@ -13,3 +13,4 @@ Name,Description,Flags,Value
 (hvdifftap.23),Space between diff or tap outside Hvi and Hvi,P,0.180
 (hvdifftap.24),Spacing of nwell to N+ Hdiff (rule exempted inside UHVI),DE NE,0.430
 (hvdifftap.25),Min space of N+ Hdiff inside HVI across non-abutting P+_tap,NC,1.070
+(hvdifftap.26),Min spacing between pwbm to difftap outside UHVI,,N/A

docs/rules/periphery/p049-hvntm_dotdash.csv

@@ -9,3 +9,4 @@ Name,Description,Flags,Value
 (hvntm.6b),"Space, no overlap, between p+_tap and hvntm along the diff-butting edge",P,0.000
 (hvntm.7),hvntm must enclose ESD_nwell_tap inside hvi by atleast,P,0.000
 (hvntm.9),Hvntm must not overlap :drc_tag:`areaid.ce`,,
+(hvntm.10),Hvntm must overlap hvi,,

docs/rules/periphery/p049-hvpoly_dotdash.csv

@@ -1,2 +1,3 @@
 Name,Description,Flags,Value
 (hvpoly.13),Min width of poly over diff inside Hvi,P,0.500
+(hvpoly.14),(poly and diff) cannot straddle Hvi,,

docs/rules/periphery/p050-denmos_dotdash.csv

@@ -13,3 +13,4 @@ Name,Description,Flags,Value
 (denmos.11),Min spacing between p+ tap and (nwell overlapping de_nFet_drain),,0.860
 (denmos.12),Min spacing between nwells overlapping de_nFET_drain,,2.400
 (denmos.13),de_nFet_source must be enclosed by nsdm by,,0.130
+(denmos.14),nvhv FETs must be enclosed by :drc_tag:`areaid.mt`,,N/A

docs/rules/periphery/p051-depmos_dotdash.csv

@@ -12,3 +12,4 @@ Name,Description,Flags,Value
 (depmos.10),Min enclosure of de_pFet_drain by nwell hole,,0.860
 (depmos.11),Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain),,0.660
 (depmos.12),de_pFet_source must be enclosed by psdm by,,0.130
+(depmos.13),pvhv fets( except those with W/L = 5.0/0.66) must be enclosed by :drc_tag:`areaid.mt`,,N/A

docs/rules/periphery/p052-extd_dotdash.csv

@@ -6,3 +6,4 @@ Name,Description,Flags,Value
 (extd.5),"Only cell name ""s8rf_n20vhviso1"" is a valid cell name for n20vhviso1 device  (Check in LVS as invalid device)",,N/A
 (extd.6),"Only cell name ""s8rf_p20vhv1"" is a valid cell name for p20vhv1 device  (Check in LVS as invalid device)",,N/A
 (extd.7),"Only cell name ""s8rf_n20nativevhv1*"" is a valid cell name for n20nativevhv1 device  (Check in LVS as invalid device)",,N/A
+(extd.8),"Only cell name ""s8rf_n20zvtvhv1*"" is a valid cell name for n20zvtvhv1 device  (Check in LVS as invalid device)",,N/A

docs/rules/periphery/p054-hv_dotdash_dotdash.csv

@@ -17,3 +17,4 @@ Name,Description,Flags,Value
 (hv.poly.6a),Min extension of poly beyond hvFET_gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
 (hv.poly.6b),Extension of hv poly beyond FET_gate (including hvFET_gate; exempt poly extending beyond diff along the S/D direction in a denmos/depmos),,0.160
 (hv.poly.7),Minimum overlap of hv poly ring_FET and diff,,
+(hv.poly.8),Any poly gate abutting hv_source/drain becomes a hvFET_gate,,

docs/rules/periphery/p055-uhvi_dotdash_dotdash.csv

@@ -8,3 +8,4 @@ Name,Description,Flags,Value
 (uhvi.7.-),natfet.dg must be enclosed by UHVI layer by at least,,N/A
 (uhvi.8.-),Minimum width of natfet.dg,,N/A
 (uhvi.9.-),Minimum Space spacing of natfet.dg,,N/A
+(uhvi.10.-),natfet.dg layer is not allowed,,N/A

docs/rules/periphery/p055-ulvt-_dotdash.csv

@@ -1,3 +1,4 @@
 Name,Description,Flags,Value
 (ulvt-.1),":drc_tag:`areaid.low_vt` must enclose dnw for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
 (ulvt-.2),":drc_tag:`areaid.low_vt` must enclose pwbm.dg for the UHV dnw-psub diode texted ""condiodeHvPsub""",,NA
+(ulvt-.3),:drc_tag:`areaid.low_vt` can not straddle UHVI,,NA

docs/rules/periphery/p055-vhvi_dotdash_dotdash.csv

@@ -12,3 +12,4 @@ Name,Description,Flags,Value
 (vhvi.5.-),Vhvi:dg cannot straddle VHVSourceDrain,,
 (vhvi.6.-),Vhvi:dg overlapping VHVSourceDrain must not overlap poly,,
 (vhvi.7.-),Vhvi:dg cannot straddle VHVPoly,,
+(vhvi.8.-),"Min space between nwell tagged with vhvi:dg and deep nwell, nwell, or n+diff on a separate net (except for n+diff overlapping nwell tagged with vhvi:dg).",,11.240

docs/rules/periphery/p056-pwres_dotdash_dotdash.csv

@@ -10,3 +10,4 @@ Name,Description,Flags,Value
 (pwres.8.-),Diff or poly is not allowed in the pwell resistor.,,
 (pwres.9.-),Nwell surrounding the pwell resistor must have a full ring of contacted tap strapped with metal.,,
 (pwres.10.-),The res layer must abut pwres_terminal on opposite and parallel edges,,
+(pwres.11.-),The res layer must abut nwell on opposite and parallel edges not checked in Rule pwres.10,,

docs/rules/periphery/p057-rfdiode_dotdash_dotdash.csv

@@ -4,4 +4,5 @@ Name,Description,Flags,Value
 (rfdiode.3.-),":drc_tag:`areaid.re` must be coincident with innwer edge of the nwell ring for the rf pwell-deep nwell diode
 Allowed PNP layout
 Layout: pnppar
-Allowed NPN layout",,
+Allowed NPN layout
+Layout: npnpar1x1",,