From 1e16594fb2c6bfe2d68b59b062249a1987add15b Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Tue, 3 Nov 2020 16:24:36 +0100 Subject: [PATCH 01/40] Removed duplicated keys from previous.rst Signed-off-by: Wojciech Gryncewicz --- docs/previous.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/docs/previous.rst b/docs/previous.rst index 2c87fcb..887518a 100644 --- a/docs/previous.rst +++ b/docs/previous.rst @@ -29,13 +29,9 @@ This section should also help people who have previously had access (under NDA) process. It stood for the "8th generation" of the SONOS technology developed originally by Cypress. - :lib_process:`s8phrc` :lib_process:`s180` The name for using 180nm technology on the 130nm process. - - :lib_process:`s8phirs` - :lib_process:`s8pfhd` The base process. 5 metal layer backend stack, 16V devices, deep nwell. From 742d1a87d04ad1bfca7439d82e629aaadf2b296a Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Fri, 27 Nov 2020 11:10:20 +0100 Subject: [PATCH 02/40] Added cell VCD waveform generator script --- environment.yml | 3 + .../skywater_pdk/cells/generate/waveform.py | 162 ++++++++++++++++++ 2 files changed, 165 insertions(+) create mode 100755 scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py diff --git a/environment.yml b/environment.yml index ee13527..08e754a 100644 --- a/environment.yml +++ b/environment.yml @@ -20,6 +20,9 @@ channels: dependencies: - python=3.8 - pip +- yosys +- netlistsvg +- verilog # Packages installed from PyPI - pip: - -r file:requirements.txt diff --git a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py new file mode 100755 index 0000000..ec3b865 --- /dev/null +++ b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py @@ -0,0 +1,162 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright 2020 The SkyWater PDK Authors. +# +# Use of this source code is governed by the Apache 2.0 +# license that can be found in the LICENSE file or at +# https://www.apache.org/licenses/LICENSE-2.0 +# +# SPDX-License-Identifier: Apache-2.0 + +''' This is a cell VCD waveform generation script. +''' + +import csv +import json +import os +import sys +import argparse +import pathlib +import glob +import subprocess +import textwrap +import re + + +def write_vcd (cellpath, define_data, use_power_pins=False): + ''' Generates vcd for a given cell. + + Args: + cellpath - path to a cell [str of pathlib.Path] + define_data - cell data from json [dic] + use_power_pins - include power pins toggling in simulation [bool] + ''' + + # collect power port names + pp = [] + for p in define_data['ports']: + if len(p)>2 and p[0]=='power': + pp.append(p[1]) + + # define output file(s) + ppsuffix = '.pp' if use_power_pins else '' + outfile = os.path.join(cellpath, define_data['file_prefix'] + ppsuffix + '.vcd') + vppfile = os.path.join(cellpath, define_data['file_prefix'] + '.vpp.tmp') + tmptestbed = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v.tmp') + + # find and patch Verilog testbed file + testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v') + assert os.path.exists(testbedfile), testbedfile + insertppdefine = use_power_pins + prvline='' + with open(tmptestbed,'w') as ttb: + with open(testbedfile,'r') as tbf: + for line in tbf: + # add use_power_pins define + if insertppdefine and line.startswith('`include'): + line = '`define USE_POWER_PINS\n' + line + insertppdefine = False + # add dumpfile define + if prvline.strip(' \n\r')=='begin': + line = line[:-len(line.lstrip())] + \ + '$dumpfile("' + outfile + '");\n' + \ + line[:-len(line.lstrip())] + \ + '$dumpvars(1,top);\n' + \ + line + # remove power pins from reg - optinal, but makes output more readable + if not use_power_pins: + for p in pp: + if re.search( 'reg\s+'+p, line ) is not None or \ + re.search( p+'\s+\=', line ) is not None : + line='' + break + # remove power pins from dut + if not use_power_pins and define_data['file_prefix']+' dut' in line: + for p in pp: + line = line.replace(f'.{p}({p}),','') + line = line.replace(f'.{p}({p}))',')') + prvline = line + ttb.write(line) + + # generate vpp code and vcd recording + if subprocess.call(['iverilog', '-o', vppfile, tmptestbed], cwd=cellpath): + raise ChildProcessError("Icarus Verilog compilation failed") + if subprocess.call(['vvp', vppfile], cwd=cellpath): + raise ChildProcessError("Icarus Verilog runtime failed") + + # remove temporary files + os.remove(tmptestbed) + os.remove(vppfile) + + +def process(cellpath): + ''' Processes cell indicated by path. + Opens cell definiton and calls further processing + + Args: + cellpath - path to a cell [str of pathlib.Path] + ''' + + print() + print(cellpath) + define_json = os.path.join(cellpath, 'definition.json') + if not os.path.exists(define_json): + print("No definition.json in", cellpath) + assert os.path.exists(define_json), define_json + define_data = json.load(open(define_json)) + + if define_data['type'] == 'cell': + write_vcd(cellpath, define_data, use_power_pins = False) + write_vcd(cellpath, define_data, use_power_pins = True) + + return + + +def main(): + ''' Generates VCD waveform for cell.''' + + prereq_txt = '' + output_txt = 'output:\n generates [fullcellname].vcd' + allcellpath = '../../../libraries/*/latest/cells/*' + + parser = argparse.ArgumentParser( + description = main.__doc__, + epilog = prereq_txt +'\n\n'+ output_txt, + formatter_class=argparse.RawDescriptionHelpFormatter) + parser.add_argument( + "--all_libs", + help="process all cells in "+allcellpath, + action="store_true") + parser.add_argument( + "cell_dir", + help="path to the cell directory", + type=pathlib.Path, + nargs="*") + + args = parser.parse_args() + + if args.all_libs: + path = pathlib.Path(allcellpath).expanduser() + parts = path.parts[1:] if path.is_absolute() else path.parts + paths = pathlib.Path(path.root).glob(str(pathlib.Path("").joinpath(*parts))) + args.cell_dir = list(paths) + + cell_dirs = [d.resolve() for d in args.cell_dir if d.is_dir()] + + errors = 0 + for d in cell_dirs: + try: + process(d) + except KeyboardInterrupt: + sys.exit(1) + except (AssertionError, FileNotFoundError, ChildProcessError) as ex: + print (f'Error: {type(ex).__name__}') + print (f'{ex.args}') + errors +=1 + print (f'\n{len(cell_dirs)} files processed, {errors} errors.') + return 0 if errors else 1 + +if __name__ == "__main__": + sys.exit(main()) + From 09197ef30e02045f7d7fcb5facf180bb3c60d9ab Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Fri, 27 Nov 2020 18:45:39 +0100 Subject: [PATCH 03/40] Changed Icarus verilog package name in environment.yml --- environment.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/environment.yml b/environment.yml index 08e754a..320a1a5 100644 --- a/environment.yml +++ b/environment.yml @@ -22,7 +22,7 @@ dependencies: - pip - yosys - netlistsvg -- verilog +- iverilog # Packages installed from PyPI - pip: - -r file:requirements.txt From 1cadc862a352ed74d6746a38ecea03893848cef2 Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Wed, 25 Nov 2020 12:00:44 +0100 Subject: [PATCH 04/40] docs: Suppressed footnote warnings for included -key.rst files Signed-off-by: Wojciech Gryncewicz --- docs/conf.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/conf.py b/docs/conf.py index b817d54..70129cb 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -124,6 +124,9 @@ exclude_patterns = [ 'code-of-conduct.rst', 'rules/periphery-rules.rst', 'rules/device-details/*/index.rst', + 'rules/summary/*-key.rst', + 'rules/layers/*-key.rst', + 'rules/hv/*-key.rst', ] # The name of the Pygments (syntax highlighting) style to use. From 2fada8d9e17a4e17f206002192c2a2f78a97a2e3 Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Wed, 25 Nov 2020 12:05:09 +0100 Subject: [PATCH 05/40] docs: Fixed a typo and table symbols explanation layout Signed-off-by: Wojciech Gryncewicz --- docs/rules/layers/table-f2a-lvs-key.rst | 1 + docs/rules/layers/table-f2b-mask-key.rst | 1 + docs/rules/summary.rst | 4 ++-- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/rules/layers/table-f2a-lvs-key.rst b/docs/rules/layers/table-f2a-lvs-key.rst index 5b1f28a..b923848 100644 --- a/docs/rules/layers/table-f2a-lvs-key.rst +++ b/docs/rules/layers/table-f2a-lvs-key.rst @@ -1,4 +1,5 @@ Explanation of symbols: + * ``-`` = Layer illegal for the device * ``+`` = Layer allowed to overlap * ``D`` = DRAWN indicates that a layer is drawn by Design. diff --git a/docs/rules/layers/table-f2b-mask-key.rst b/docs/rules/layers/table-f2b-mask-key.rst index ddbb215..6ebbc21 100644 --- a/docs/rules/layers/table-f2b-mask-key.rst +++ b/docs/rules/layers/table-f2b-mask-key.rst @@ -1,4 +1,5 @@ Explanation of symbols: + * ``-`` = Layer not created for the device * ``+`` = Layer allowed to overlap * ``C`` = CREATED diff --git a/docs/rules/summary.rst b/docs/rules/summary.rst index 0e99e4e..7ad4313 100644 --- a/docs/rules/summary.rst +++ b/docs/rules/summary.rst @@ -1,5 +1,5 @@ -Summry of Key Periphery Rules -============================= +Summary of Key Periphery Rules +============================== .. csv-table:: Table F3a: Front end layers (Low Voltage Devices) :file: summary/table-f3a-font-end-low-voltage.csv From c7c5dd8a5080eba3a6b86d5ab34d19ae0a9cfaee Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Mon, 30 Nov 2020 18:40:38 +0100 Subject: [PATCH 06/40] VCD to wavedrom JSON/SVG converter Signed-off-by: Wojciech Gryncewicz --- requirements.txt | 1 + .../cells/generate/vcd2wavedrom.py | 225 ++++++++++++++++++ 2 files changed, 226 insertions(+) create mode 100755 scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py diff --git a/requirements.txt b/requirements.txt index fe8a2c1..41b39cc 100644 --- a/requirements.txt +++ b/requirements.txt @@ -1,4 +1,5 @@ flake8 +wavedrom # rst_include tool as GitHub doesn't support `.. include::` when rendering # previews. diff --git a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py new file mode 100755 index 0000000..69f3ef4 --- /dev/null +++ b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py @@ -0,0 +1,225 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright 2020 The SkyWater PDK Authors. +# +# Use of this source code is governed by the Apache 2.0 +# license that can be found in the LICENSE file or at +# https://www.apache.org/licenses/LICENSE-2.0 +# +# SPDX-License-Identifier: Apache-2.0 + +''' VCD waveform to wawedrom script/SVG conversion script. +''' + +from __future__ import print_function +import os +import sys +import argparse +import pathlib +import wavedrom +from contextlib import contextmanager + + +wavedrom_template ="""\ +{{ signal: [ +{signals} +]}}""" + +signal_template = " {{ name: \"{name}\", {fill}wave: '{wave}' }}" + +def eprint(*args, **kwargs): + ''' Print to stderr ''' + print(*args, file=sys.stderr, **kwargs) + +@contextmanager +def file_or_stdout(file): + ''' Open file or stdout if file is None + ''' + if file is None: + yield sys.stdout + else: + with file.open('w') as out_file: + yield out_file + + +def readVCD (file): + ''' Parses VCD file. + + Args: + file - path to a VCD file [pathlib.Path] + + Returns: + vcd - dictionary containing vcd sections [dict] + ''' + eprint() + eprint(file.name) + assert file.is_file(), file + + vcd = {} + with file.open('r') as f: + currtag = 'body' + for line in f: + # regular line + if not line.startswith('$'): + vcd[currtag] = vcd.setdefault(currtag, '') + line + continue + # tag, other than end + if not line.startswith('$end'): + currtag = line.partition(' ')[0].lstrip('$').rstrip() + vcd[currtag] = vcd.setdefault(currtag, '') + line.partition(' ')[2].rpartition('$')[0] + # line ends with end tag + if not vcd[currtag].endswith('\n'): + vcd[currtag] += '\n' + if line.split()[-1]=='$end': + currtag = 'body' + vcd[currtag] = '' + + if 'var' not in vcd or 'dumpvars' not in vcd: + raise SyntaxError("Invalid VCD file format") + + return vcd + +def parsetowavedrom (file, savetofile = False): + ''' Reads and simplifies VCD waveform + Generates wavedrom notation. + + Args: + file - path to a VCD file [pathlib.Path] + + ''' + varsubst = {} # var substitution + reg = [] # list of signals + wire = [] # list of signals (wire class) + wave = {} # waveform + event = [] # event timings + + vcd = readVCD (file) + + # parse vars + for line in vcd['var'].split('\n'): + line = line.strip().split() + if len(line)<4: + if len(line): + print (f"Warning: malformed var definition {' '.join(line)}") + continue + if line[1]!='1': + print (f"Warning: bus in vars (unsupported) {' '.join(line)}") + if line[0]=='reg': + reg.append(line[3]) + varsubst[line[2]] = line[3] + if line[0]=='wire': + wire.append(line[3]) + varsubst[line[2]] = line[3] + + # set initial states + event.append(0) + #default + for v in reg+wire: + wave[v] = ['x'] + #defined + for line in vcd['dumpvars'].split('\n'): + if len(line)>=2: + wave[ varsubst[line[1]] ] = [line[0]] + + # parse wave body + for line in vcd['body'].split('\n'): + #timestamp line + if line.startswith('#'): + line = line.strip().lstrip('#') + if not line.isnumeric(): + raise SyntaxError("Invalid VCD timestamp") + event.append(int(line)) + for v in wave.keys(): + wave[v].append('.') + # state change line + else : + if len(line)>=2: + wave [ varsubst[line[1]] ][-1] = line[0] + + # TODO: add "double interval support" + + signals = [] + for v in wave.keys(): + fill = ' ' * (max( [len(s) for s in wave.keys()] ) - len(v)) + wavestr = ''.join(wave[v]) + signals.append( signal_template.format( name = v, wave = wavestr, fill = fill ) ) + signals = ',\n'.join(signals) + + wavedrom = wavedrom_template.format ( signals = signals ) + + outfile = file.with_suffix(".wdr.json") if savetofile else None + with file_or_stdout(outfile) as f: + f.write(wavedrom) + + return wavedrom + +def quoted_strings_wavedrom (wdr) : + ''' Convert wavedrom script to more restrictive + version of JSON with quoted keywords + ''' + wdr = wdr.replace(' signal:',' "signal":') + wdr = wdr.replace(' name:',' "name":') + wdr = wdr.replace(' wave:',' "wave":') + wdr = wdr.replace("'",'"') + return wdr + +def main(): + ''' Converts VCD waveform to wavedrom format''' + output_txt = 'output:\n stdout or [vcdname].wdr.json file and/or [vcdname].svg file' + allcellpath = '../../../libraries/*/latest/cells/*/*.vcd' + + parser = argparse.ArgumentParser( + description = main.__doc__, + epilog = output_txt, + formatter_class=argparse.RawDescriptionHelpFormatter) + parser.add_argument( + "--all_libs", + help="process all in "+allcellpath, + action="store_true") + parser.add_argument( + "-w", + "--wavedrom", + help="generate wavedrom .wdr.json file", + action="store_true") + parser.add_argument( + "-s", + "--savesvg", + help="generate .svg image", + action="store_true") + parser.add_argument( + "infile", + help="VCD waveform file", + type=pathlib.Path, + nargs="*") + + args = parser.parse_args() + + if args.all_libs: + path = pathlib.Path(allcellpath).expanduser() + parts = path.parts[1:] if path.is_absolute() else path.parts + paths = pathlib.Path(path.root).glob(str(pathlib.Path("").joinpath(*parts))) + args.infile = list(paths) + + infile = [d.resolve() for d in args.infile if d.is_file()] + + errors = 0 + for f in infile: + try: + wdr = parsetowavedrom(f, args.wavedrom) + if args.savesvg: + svg = wavedrom.render( quoted_strings_wavedrom(wdr) ) + outfile = f.with_suffix(".svg") + svg.saveas(outfile) + except KeyboardInterrupt: + sys.exit(1) + except (AssertionError, FileNotFoundError, ChildProcessError) as ex: + eprint (f'Error: {type(ex).__name__}') + eprint (f'{ex.args}') + errors +=1 + eprint (f'\n{len(infile)} files processed, {errors} errors.') + return 0 if errors else 1 + +if __name__ == "__main__": + sys.exit(main()) + From adea4260e7579250f15719e3dd801c3570abf949 Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Tue, 1 Dec 2020 13:44:17 +0100 Subject: [PATCH 07/40] Improved handling of testbenches with infinite clock Signed-off-by: Wojciech Gryncewicz --- .../skywater_pdk/cells/generate/vcd2wavedrom.py | 12 +++++++----- .../skywater_pdk/cells/generate/waveform.py | 9 ++++++++- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py index 69f3ef4..ed9b43b 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py +++ b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py @@ -75,8 +75,11 @@ def readVCD (file): currtag = 'body' vcd[currtag] = '' - if 'var' not in vcd or 'dumpvars' not in vcd: - raise SyntaxError("Invalid VCD file format") + if 'var' not in vcd: + raise SyntaxError("No variables recorded in VCD file") + if 'dumpvars' not in vcd: + print ("Warning: intial variable states undefined") + var['dumpvars'] = '' return vcd @@ -213,9 +216,8 @@ def main(): svg.saveas(outfile) except KeyboardInterrupt: sys.exit(1) - except (AssertionError, FileNotFoundError, ChildProcessError) as ex: - eprint (f'Error: {type(ex).__name__}') - eprint (f'{ex.args}') + except (SyntaxError, AssertionError, FileNotFoundError, ChildProcessError) as ex: + eprint (f'{type(ex).__name__}: {", ".join(ex.args)}') errors +=1 eprint (f'\n{len(infile)} files processed, {errors} errors.') return 0 if errors else 1 diff --git a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py index ec3b865..a21d2ad 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py +++ b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/waveform.py @@ -49,6 +49,8 @@ def write_vcd (cellpath, define_data, use_power_pins=False): testbedfile = os.path.join(cellpath, define_data['file_prefix'] + '.tb.v') assert os.path.exists(testbedfile), testbedfile insertppdefine = use_power_pins + insertdumpvars = True + insertfinish = True prvline='' with open(tmptestbed,'w') as ttb: with open(testbedfile,'r') as tbf: @@ -58,12 +60,17 @@ def write_vcd (cellpath, define_data, use_power_pins=False): line = '`define USE_POWER_PINS\n' + line insertppdefine = False # add dumpfile define - if prvline.strip(' \n\r')=='begin': + if insertdumpvars and prvline.strip(' \n\r')=='begin': line = line[:-len(line.lstrip())] + \ '$dumpfile("' + outfile + '");\n' + \ line[:-len(line.lstrip())] + \ '$dumpvars(1,top);\n' + \ line + insertdumpvars = False + # add finish command, to stop paraller threads + if insertfinish and line.strip(' \n\r')=='end' and not '$finish' in prvline: + line = prvline[:-len(prvline.lstrip())] + '$finish;\n' + line + insertfinish = False # remove power pins from reg - optinal, but makes output more readable if not use_power_pins: for p in pp: From c5bd980a84ed99d427f08721619727ecff7cfa0e Mon Sep 17 00:00:00 2001 From: Wojciech Gryncewicz Date: Tue, 1 Dec 2020 15:26:39 +0100 Subject: [PATCH 08/40] Added option for reduction of long clock sequences in wavedrom converter Signed-off-by: Wojciech Gryncewicz --- .../cells/generate/vcd2wavedrom.py | 70 ++++++++++++++----- 1 file changed, 53 insertions(+), 17 deletions(-) diff --git a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py index ed9b43b..7e4adf1 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py +++ b/scripts/python-skywater-pdk/skywater_pdk/cells/generate/vcd2wavedrom.py @@ -18,6 +18,7 @@ import sys import argparse import pathlib import wavedrom +import re from contextlib import contextmanager @@ -44,7 +45,7 @@ def file_or_stdout(file): def readVCD (file): - ''' Parses VCD file. + ''' Parses VCD file. Args: file - path to a VCD file [pathlib.Path] @@ -67,12 +68,12 @@ def readVCD (file): # tag, other than end if not line.startswith('$end'): currtag = line.partition(' ')[0].lstrip('$').rstrip() - vcd[currtag] = vcd.setdefault(currtag, '') + line.partition(' ')[2].rpartition('$')[0] + vcd[currtag] = vcd.setdefault(currtag, '') + line.partition(' ')[2].rpartition('$')[0] # line ends with end tag if not vcd[currtag].endswith('\n'): - vcd[currtag] += '\n' + vcd[currtag] += '\n' if line.split()[-1]=='$end': - currtag = 'body' + currtag = 'body' vcd[currtag] = '' if 'var' not in vcd: @@ -83,13 +84,39 @@ def readVCD (file): return vcd -def parsetowavedrom (file, savetofile = False): + +def reduce_clock_sequences (wave) : + ''' Remove clock seqnces longer than 2 cycles + not accompanied by other signals changes + + Parameters: + wave - dictionary 'signal'->['list of states'] [dict] + ''' + for v in wave: + sig = wave[v] # analized signal + other = [wave[i] for i in wave if i!=v] # list of other signals + other = [''.join(s) for s in zip(*other)] # list of concatenated states + other = [len(s.replace('.','')) for s in other] # list of state changes count + sig = [s if o==0 else ' ' for s,o in zip(sig,other)] # keep only when no changes in other + sig = "".join(sig) + cuts = [] + for m in re.finditer("(10){2,}",sig): + cuts.append( (m.start()+1, m.end()-1) ) # area to be reduced, leave 1..0 + cuts.reverse() + for cut in cuts: + for v,w in wave.items(): # reduce cuts from all signals + wave[v] = w[ :cut[0]] + w[cut[1]: ] + + return wave + + +def parsetowavedrom (file, savetofile = False, reduce_clock = False): ''' Reads and simplifies VCD waveform Generates wavedrom notation. Args: file - path to a VCD file [pathlib.Path] - + ''' varsubst = {} # var substitution reg = [] # list of signals @@ -117,21 +144,21 @@ def parsetowavedrom (file, savetofile = False): # set initial states event.append(0) - #default + #default for v in reg+wire: wave[v] = ['x'] #defined - for line in vcd['dumpvars'].split('\n'): + for line in vcd['dumpvars'].split('\n'): if len(line)>=2: wave[ varsubst[line[1]] ] = [line[0]] - # parse wave body + # parse wave body for line in vcd['body'].split('\n'): #timestamp line if line.startswith('#'): line = line.strip().lstrip('#') if not line.isnumeric(): - raise SyntaxError("Invalid VCD timestamp") + raise SyntaxError("Invalid VCD timestamp") event.append(int(line)) for v in wave.keys(): wave[v].append('.') @@ -139,11 +166,12 @@ def parsetowavedrom (file, savetofile = False): else : if len(line)>=2: wave [ varsubst[line[1]] ][-1] = line[0] - - # TODO: add "double interval support" + + if reduce_clock: + wave = reduce_clock_sequences(wave) signals = [] - for v in wave.keys(): + for v in wave.keys(): fill = ' ' * (max( [len(s) for s in wave.keys()] ) - len(v)) wavestr = ''.join(wave[v]) signals.append( signal_template.format( name = v, wave = wavestr, fill = fill ) ) @@ -151,15 +179,18 @@ def parsetowavedrom (file, savetofile = False): wavedrom = wavedrom_template.format ( signals = signals ) - outfile = file.with_suffix(".wdr.json") if savetofile else None + outfile = file.with_suffix(".wdr.json") if savetofile else None with file_or_stdout(outfile) as f: f.write(wavedrom) - + return wavedrom def quoted_strings_wavedrom (wdr) : ''' Convert wavedrom script to more restrictive version of JSON with quoted keywords + + Parameters: + wdr - wavedrom script [str] ''' wdr = wdr.replace(' signal:',' "signal":') wdr = wdr.replace(' name:',' "name":') @@ -190,6 +221,11 @@ def main(): "--savesvg", help="generate .svg image", action="store_true") + parser.add_argument( + "-r", + "--reduceclk", + help="reduce clock sequences", + action="store_true") parser.add_argument( "infile", help="VCD waveform file", @@ -209,10 +245,10 @@ def main(): errors = 0 for f in infile: try: - wdr = parsetowavedrom(f, args.wavedrom) + wdr = parsetowavedrom(f, args.wavedrom, args.reduceclk) if args.savesvg: svg = wavedrom.render( quoted_strings_wavedrom(wdr) ) - outfile = f.with_suffix(".svg") + outfile = f.with_suffix(".svg") svg.saveas(outfile) except KeyboardInterrupt: sys.exit(1) From d99d853ef990df7d5589dc4c8ce69d9745f33367 Mon Sep 17 00:00:00 2001 From: Rob Taylor Date: Sun, 20 Dec 2020 23:19:31 +0000 Subject: [PATCH 09/40] Faster version of liberty_float - gives a 25% to 50% speedup This also fixes a bug in liberty_float for numbers with a magnitute between 9 and 15. Previously: >>> liberty_float(1e15) '1000000000000000' >>> liberty_float(1e10) '10000000000.' >>> liberty_float(1e9) '1000000000.0' >>> liberty_float(1e16) '1.000000e+16' Now: >>> liberty_float(1e15) '1.000000e+15' >>> liberty_float(1e10) '1.000000e+10' >>> liberty_float(1e9) '1000000000.0' >>> liberty_float(1e16) '1.000000e+16' --- .../skywater_pdk/liberty.py | 36 ++++++++----------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/scripts/python-skywater-pdk/skywater_pdk/liberty.py b/scripts/python-skywater-pdk/skywater_pdk/liberty.py index 6cbda80..b14ec3e 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/liberty.py +++ b/scripts/python-skywater-pdk/skywater_pdk/liberty.py @@ -31,12 +31,15 @@ from collections import defaultdict from typing import Tuple, List, Dict +from math import frexp, log2 + from . import sizes from .utils import sortable_extracted_numbers debug = False +LOG2_10 = log2(10) class TimingType(enum.IntFlag): """ @@ -792,36 +795,25 @@ def liberty_float(f): """ try: - f2 = float(f) + r = float(f) except (ValueError, TypeError): - f2 = None + r = None if isinstance(f, bool): - f2 = None + r = None - if f is None or f2 != f: + if f is None or r != f: raise ValueError("%r is not a float" % f) - WIDTH = len(str(0.0083333333)) + width = 11 - s = json.dumps(f) - if 'e' in s: - a, b = s.split('e') - if '.' not in a: - a += '.' - while len(a)+len(b)+1 < WIDTH: - a += '0' - s = "%se%s" % (a, b) - elif '.' in s: - while len(s) < WIDTH: - s += '0' + mag = int(frexp(r)[1]/LOG2_10) + if mag > 9: + return f'%{width}e' % r + if mag < 0: + return f"%{width+1}.{width-1}f" % r else: - if len(s) < WIDTH: - s += '.' - while len(s) < WIDTH: - s += '0' - return s - + return f"%{width+1}.{width-mag-1}f" % r LIBERTY_ATTRIBUTE_TYPES = { 'boolean': liberty_bool, From 9d39c63f51ae10807711fe5be5e4baa796519b45 Mon Sep 17 00:00:00 2001 From: Rob Taylor Date: Mon, 21 Dec 2020 23:33:09 +0000 Subject: [PATCH 10/40] Add doctests for liberty_float edge case Issue #280 --- scripts/python-skywater-pdk/skywater_pdk/liberty.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/scripts/python-skywater-pdk/skywater_pdk/liberty.py b/scripts/python-skywater-pdk/skywater_pdk/liberty.py index b14ec3e..77f2bb5 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/liberty.py +++ b/scripts/python-skywater-pdk/skywater_pdk/liberty.py @@ -769,6 +769,15 @@ def liberty_float(f): >>> liberty_float(1) '1.0000000000' + >>> liberty_float(1e9) + '1000000000.0' + + >>> liberty_float(1e10) + '1.000000e+10' + + >>> liberty_float(1e15) + '1.000000e+15' + >>> liberty_float(True) Traceback (most recent call last): ... From 0f52bdcfbf44fabb1957984ab668c467f59fb334 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 16 Feb 2021 11:35:57 -0800 Subject: [PATCH 11/40] Convert submodule sources to be github versions. Signed-off-by: Tim 'mithro' Ansell --- .gitmodules | 76 ++++++++++++++++++++++++++--------------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/.gitmodules b/.gitmodules index e02f407..872c42d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,61 +1,61 @@ # sky130_fd_pr [submodule "libraries/sky130_fd_pr/latest"] path = libraries/sky130_fd_pr/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = master shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.20.1"] path = libraries/sky130_fd_pr/v0.20.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.20.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.20.0"] path = libraries/sky130_fd_pr/v0.20.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.20.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.13.0"] path = libraries/sky130_fd_pr/v0.13.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.13.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.12.1"] path = libraries/sky130_fd_pr/v0.12.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.12.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.12.0"] path = libraries/sky130_fd_pr/v0.12.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.12.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.11.0"] path = libraries/sky130_fd_pr/v0.11.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.11.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.10.1"] path = libraries/sky130_fd_pr/v0.10.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.10.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.10.0"] path = libraries/sky130_fd_pr/v0.10.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.10.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.0.9"] path = libraries/sky130_fd_pr/v0.0.9 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_pr.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git branch = branch-0.0.9 shallow = true fetchRecurseSubmodules = false @@ -63,36 +63,36 @@ # sky130_fd_sc_hd [submodule "libraries/sky130_fd_sc_hd/latest"] path = libraries/sky130_fd_sc_hd/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git branch = master shallow = true [submodule "libraries/sky130_fd_sc_hd/v0.0.2"] path = libraries/sky130_fd_sc_hd/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git branch = branch-0.0.2 shallow = true [submodule "libraries/sky130_fd_sc_hd/v0.0.1"] path = libraries/sky130_fd_sc_hd/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git branch = branch-0.0.1 shallow = true # sky130_fd_sc_hdll [submodule "libraries/sky130_fd_sc_hdll/latest"] path = libraries/sky130_fd_sc_hdll/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hdll/v0.1.1"] path = libraries/sky130_fd_sc_hdll/v0.1.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git branch = branch-0.1.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_hdll/v0.1.0"] path = libraries/sky130_fd_sc_hdll/v0.1.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hdll.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git branch = branch-0.1.0 shallow = true fetchRecurseSubmodules = false @@ -100,19 +100,19 @@ # sky130_fd_sc_hs [submodule "libraries/sky130_fd_sc_hs/latest"] path = libraries/sky130_fd_sc_hs/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hs/v0.0.2"] path = libraries/sky130_fd_sc_hs/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git branch = branch-0.0.2 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_hs/v0.0.1"] path = libraries/sky130_fd_sc_hs/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hs.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false @@ -120,19 +120,19 @@ # sky130_fd_sc_ms [submodule "libraries/sky130_fd_sc_ms/latest"] path = libraries/sky130_fd_sc_ms/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_ms/v0.0.2"] path = libraries/sky130_fd_sc_ms/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git branch = branch-0.0.2 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_ms/v0.0.1"] path = libraries/sky130_fd_sc_ms/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ms.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false @@ -140,19 +140,19 @@ # sky130_fd_sc_ls [submodule "libraries/sky130_fd_sc_ls/latest"] path = libraries/sky130_fd_sc_ls/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_ls/v0.1.1"] path = libraries/sky130_fd_sc_ls/v0.1.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git branch = branch-0.1.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_ls/v0.1.0"] path = libraries/sky130_fd_sc_ls/v0.1.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_ls.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git branch = branch-0.1.0 shallow = true fetchRecurseSubmodules = false @@ -160,19 +160,19 @@ # sky130_fd_sc_lp [submodule "libraries/sky130_fd_sc_lp/latest"] path = libraries/sky130_fd_sc_lp/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_lp/v0.0.2"] path = libraries/sky130_fd_sc_lp/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git branch = branch-0.0.2 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_lp/v0.0.1"] path = libraries/sky130_fd_sc_lp/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_lp.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false @@ -180,25 +180,25 @@ # sky130_fd_sc_hvl [submodule "libraries/sky130_fd_sc_hvl/latest"] path = libraries/sky130_fd_sc_hvl/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hvl/v0.0.3"] path = libraries/sky130_fd_sc_hvl/v0.0.3 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git branch = branch-0.0.3 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_hvl/v0.0.2"] path = libraries/sky130_fd_sc_hvl/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git branch = branch-0.0.2 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_sc_hvl/v0.0.1"] path = libraries/sky130_fd_sc_hvl/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hvl.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false @@ -206,37 +206,37 @@ # sky130_fd_io [submodule "libraries/sky130_fd_io/latest"] path = libraries/sky130_fd_io/latest - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = master shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_io/v0.2.1"] path = libraries/sky130_fd_io/v0.2.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = branch-0.2.1 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_io/v0.2.0"] path = libraries/sky130_fd_io/v0.2.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = branch-0.2.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_io/v0.1.0"] path = libraries/sky130_fd_io/v0.1.0 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = branch-0.1.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_io/v0.0.2"] path = libraries/sky130_fd_io/v0.0.2 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = branch-0.1.0 shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_io/v0.0.1"] path = libraries/sky130_fd_io/v0.0.1 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_io.git + url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false From e72e0c57755ae308124fdca96b249965a2170898 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Fri, 23 Apr 2021 18:56:27 -0700 Subject: [PATCH 12/40] Update branch name to main. Signed-off-by: Tim 'mithro' Ansell --- .gitmodules | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/.gitmodules b/.gitmodules index 959a2b2..0874f66 100644 --- a/.gitmodules +++ b/.gitmodules @@ -6,7 +6,7 @@ [submodule "libraries/sky130_fd_pr/latest"] path = libraries/sky130_fd_pr/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = false [submodule "libraries/sky130_fd_pr/v0.20.1"] @@ -68,7 +68,7 @@ [submodule "libraries/sky130_fd_sc_hd/latest"] path = libraries/sky130_fd_sc_hd/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd.git - branch = master + branch = main shallow = true [submodule "libraries/sky130_fd_sc_hd/v0.0.2"] path = libraries/sky130_fd_sc_hd/v0.0.2 @@ -85,7 +85,7 @@ [submodule "libraries/sky130_fd_sc_hdll/latest"] path = libraries/sky130_fd_sc_hdll/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hdll.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hdll/v0.1.1"] @@ -105,7 +105,7 @@ [submodule "libraries/sky130_fd_sc_hs/latest"] path = libraries/sky130_fd_sc_hs/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hs.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hs/v0.0.2"] @@ -125,7 +125,7 @@ [submodule "libraries/sky130_fd_sc_ms/latest"] path = libraries/sky130_fd_sc_ms/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ms.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_ms/v0.0.2"] @@ -145,7 +145,7 @@ [submodule "libraries/sky130_fd_sc_ls/latest"] path = libraries/sky130_fd_sc_ls/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_ls.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_ls/v0.1.1"] @@ -165,7 +165,7 @@ [submodule "libraries/sky130_fd_sc_lp/latest"] path = libraries/sky130_fd_sc_lp/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_lp.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_lp/v0.0.2"] @@ -185,7 +185,7 @@ [submodule "libraries/sky130_fd_sc_hvl/latest"] path = libraries/sky130_fd_sc_hvl/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hvl.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_sc_hvl/v0.0.3"] @@ -211,7 +211,7 @@ [submodule "libraries/sky130_fd_io/latest"] path = libraries/sky130_fd_io/latest url = https://github.com/google/skywater-pdk-libs-sky130_fd_io.git - branch = master + branch = main shallow = true fetchRecurseSubmodules = true [submodule "libraries/sky130_fd_io/v0.2.1"] From dac0871c34edff55670987e42befa5f1bcd59956 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 28 Apr 2021 18:52:53 -0700 Subject: [PATCH 13/40] Initialize all the library submodules. Fixes #321. Signed-off-by: Tim 'mithro' Ansell --- scripts/make/git.mk | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/scripts/make/git.mk b/scripts/make/git.mk index e1a862e..c36a296 100644 --- a/scripts/make/git.mk +++ b/scripts/make/git.mk @@ -21,19 +21,24 @@ ifeq (,$(FULL_VERSION)) $(error "Version value could not be determined. Make sure you fetch the tags.") endif -submodules: libraries/sky130_fd_sc_hd/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_hdll/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_hs/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_ms/$(SUBMODULE_VERSION)/.git libraries/sky130_fd_sc_ls/$(SUBMODULE_VERSION)/.git +LIBRARIES = $(sort $(notdir $(wildcard libraries/sky130_*))) -libraries/sky130_fd_sc_hd/%/.git: .gitmodules - git submodule update --init $(@D) +LIBS_DOT_GIT = $(addsuffix /$(SUBMODULE_VERSION)/.git,$(addprefix libraries/,$(LIBRARIES))) -libraries/sky130_fd_sc_hdll/%/.git: .gitmodules - git submodule update --init $(@D) +libraries-info: + @echo "The following libraries exist:" + @for L in $(LIBRARIES); do \ + LD=libraries/$$L/$(SUBMODULE_VERSION); \ + echo " * $$L"; \ + echo " $$(git submodule status $$LD)"; \ + done + @echo $(LIBS_DOT_GIT) -libraries/sky130_fd_sc_hs/%/.git: .gitmodules - git submodule update --init $(@D) +submodules: $(LIBS_DOT_GIT) -libraries/sky130_fd_sc_ms/%/.git: .gitmodules - git submodule update --init $(@D) +define LIB_template +libraries/$(1)/%/.git: .gitmodules + git submodule update --init $$(@D) +endef -libraries/sky130_fd_sc_ls/%/.git: .gitmodules - git submodule update --init $(@D) +$(foreach lib,$(LIBRARIES), $(eval $(call LIB_template,$(lib)))) From 04968deacd69914edbe77780426ce0a8f074373a Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 28 Apr 2021 18:39:20 -0700 Subject: [PATCH 14/40] Rename value in top Makefile so it doesn't conflict. `LIBRARIES` in the top Makefile would conflict with `LIBRARIES` in the `scripts/make/git.mk`. Signed-off-by: Tim 'mithro' Ansell --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 1896b7e..ae7d4f7 100644 --- a/Makefile +++ b/Makefile @@ -79,9 +79,9 @@ all: README.rst @true -LIBRARIES = $(sort $(notdir $(wildcard libraries/sky130_*_sc_*))) +SC_LIBS = $(sort $(notdir $(wildcard libraries/sky130_*_sc_*))) -$(LIBRARIES): | $(CONDA_ENV_PYTHON) +$(SC_LIBS): | $(CONDA_ENV_PYTHON) @$(IN_CONDA_ENV) for V in libraries/$@/*; do \ if [ -d "$$V/cells" ]; then \ python -m skywater_pdk.liberty $$V; \ @@ -99,7 +99,7 @@ sky130_fd_sc_ms-leakage: | $(CONDA_ENV_PYTHON) sky130_fd_sc_ms: sky130_fd_sc_ms-leakage -timing: $(LIBRARIES) | $(CONDA_ENV_PYTHON) +timing: $(SC_LIBS) | $(CONDA_ENV_PYTHON) @true From cc1db3eb708f74a9f2c98cec9bb6d8cd4e48af30 Mon Sep 17 00:00:00 2001 From: Mohamed Gaber Date: Thu, 5 Aug 2021 17:32:19 +0200 Subject: [PATCH 15/40] Work Around pypa/pip#10237 --- docs/environment.yml | 2 +- environment.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/environment.yml b/docs/environment.yml index 23797fd..cef4cf1 100644 --- a/docs/environment.yml +++ b/docs/environment.yml @@ -25,4 +25,4 @@ dependencies: - netlistsvg # Packages installed from PyPI - pip: - - -r file:requirements.txt + - -r requirements.txt diff --git a/environment.yml b/environment.yml index ee13527..9bd7bea 100644 --- a/environment.yml +++ b/environment.yml @@ -22,4 +22,4 @@ dependencies: - pip # Packages installed from PyPI - pip: - - -r file:requirements.txt + - -r requirements.txt From 80cf294140704292b662e7732a50c82103a81d57 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Tue, 28 Sep 2021 15:07:13 -0700 Subject: [PATCH 16/40] Update documentation on build space from sp to bd It was decided that sp is too close to single port, and should be renamed bd to reference the build space. Closes #338 --- docs/contents/libraries.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/contents/libraries.rst b/docs/contents/libraries.rst index ca3c24e..b7b29de 100644 --- a/docs/contents/libraries.rst +++ b/docs/contents/libraries.rst @@ -34,7 +34,7 @@ All sections are **lower case** and separated by an **underscore**. The sections +--------------------------------+---------------------------------------+ | Digital Standard Cells | :lib_type:`sc` | +--------------------------------+---------------------------------------+ - | Build Space (Flash, SRAM, etc) | :lib_type:`sp` | + | Build Space (Flash, SRAM, etc) | :lib_type:`bd` | +--------------------------------+---------------------------------------+ | IO and Periphery | :lib_type:`io` | +--------------------------------+---------------------------------------+ From 0512ef68902ffb6fd756b906643aed97584b6b1e Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 5 Oct 2020 06:45:35 -0700 Subject: [PATCH 17/40] docs: Fix nfet_05v0_nvt cell name. Signed-off-by: Tim 'mithro' Ansell --- docs/rules/device-details/nfet_05v0_nvt/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/rules/device-details/nfet_05v0_nvt/index.rst b/docs/rules/device-details/nfet_05v0_nvt/index.rst index a44a233..e516f22 100644 --- a/docs/rules/device-details/nfet_05v0_nvt/index.rst +++ b/docs/rules/device-details/nfet_05v0_nvt/index.rst @@ -4,7 +4,7 @@ Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Cell Name: :cell:`sky130_fd_pr__nfet_05v0_nvt` - Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt` Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt` From f198a3337bcb81401c6a3f439d02c7b3b96d36a6 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sat, 30 Oct 2021 16:11:44 -0700 Subject: [PATCH 18/40] Remove symbolator requirement. Signed-off-by: Tim 'mithro' Ansell --- docs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index f20b3a6..43d2ef2 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -10,7 +10,7 @@ sphinx-verilog-domain sphinxcontrib-hdl-diagrams # Module diagrams -git+https://github.com/SymbiFlow/symbolator.git#egg=symbolator +#git+https://github.com/SymbiFlow/symbolator.git#egg=symbolator # pycairo # vext.gi From 8da028387b0d21e0e9340e6a5278ac858f37f8d2 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sat, 30 Oct 2021 17:38:50 -0700 Subject: [PATCH 19/40] Remove conda-forge from environment channels. Signed-off-by: Tim 'mithro' Ansell --- docs/environment.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/environment.yml b/docs/environment.yml index cef4cf1..c8db8b8 100644 --- a/docs/environment.yml +++ b/docs/environment.yml @@ -16,7 +16,6 @@ name: skywater-pdk-docs channels: - symbiflow -- conda-forge - defaults dependencies: - python=3.8 From 3c78bc9c6152d4678bce1840c81287ec67759bb4 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 1 Nov 2021 07:59:38 -0700 Subject: [PATCH 20/40] Install the skywater-pdk Python library into Sphinx environment. Signed-off-by: Tim 'mithro' Ansell --- docs/environment.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/environment.yml b/docs/environment.yml index c8db8b8..7100f6f 100644 --- a/docs/environment.yml +++ b/docs/environment.yml @@ -25,3 +25,4 @@ dependencies: # Packages installed from PyPI - pip: - -r requirements.txt + - ../scripts/python-skywater-pdk From 909d06d4f6d0f40e48ae12d25640cadd328ad869 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sat, 30 Oct 2021 17:39:17 -0700 Subject: [PATCH 21/40] Update to new Sphinx theme. Signed-off-by: Tim 'mithro' Ansell --- docs/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/requirements.txt b/docs/requirements.txt index 43d2ef2..056d192 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,4 @@ -git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme +git+https://github.com/SymbiFlow/sphinx_symbiflow_theme.git#egg=sphinx-symbiflow-theme docutils sphinx From b72fa4b71424c151150e3f3a6eec04952dcedd50 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 1 Nov 2021 08:00:01 -0700 Subject: [PATCH 22/40] Updating the Sphinx configuration for new theme. Signed-off-by: Tim 'mithro' Ansell --- docs/conf.py | 55 ++++++++++++---------------------------------------- 1 file changed, 12 insertions(+), 43 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index 70129cb..8b39adb 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -152,53 +152,22 @@ html_theme = "sphinx_symbiflow_theme" # Theme options are theme-specific and customize the look and feel of a theme # further. For a list of options available for each theme, see the # documentation. -# +# https://sphinx-symbiflow-theme.readthedocs.io/en/latest/customization.html html_theme_options = { - # Specify a list of menu in Header. - # Tuples forms: - # ('Name', 'external url or path of pages in the document', boolean, 'icon name') - # - # Third argument: - # True indicates an external link. - # False indicates path of pages in the document. - # - # Fourth argument: - # Specify the icon name. - # For details see link. - # https://material.io/icons/ - 'header_links': [ - ('Home', 'index', False, 'home'), - ("GitHub", "https://github.com/google/skywater-pdk", True, 'code'), - ("SkyWater", "https://www.skywatertechnology.com/", True, 'link'), - ], + 'color_primary': 'light-green', + 'color_accent': 'teal', - # Customize css colors. - # For details see link. - # https://getmdl.io/customize/index.html - # - # Values: amber, blue, brown, cyan deep_orange, deep_purple, green, grey, indigo, light_blue, - # light_green, lime, orange, pink, purple, red, teal, yellow(Default: indigo) - 'primary_color': 'light_green', - # Values: Same as primary_color. (Default: pink) - 'accent_color': 'teal', + # Set the repo location to get a badge with stats + 'github_url': 'https://github.com/google/skywater-pdk', + 'repo_name': 'google/skywater-pdk', - # Customize layout. - # For details see link. - # https://getmdl.io/components/index.html#layout-section - 'fixed_drawer': True, - 'fixed_header': True, - 'header_waterfall': True, - 'header_scroll': False, +# 'nav_links': [ +# ('Home', 'index', False, 'home'), +# ("GitHub", "https://github.com/google/skywater-pdk", True, 'code'), +# ("SkyWater", "https://www.skywatertechnology.com/", True, 'link'), +# ], - # Render title in header. - # Values: True, False (Default: False) - 'show_header_title': False, - # Render title in drawer. - # Values: True, False (Default: True) - 'show_drawer_title': True, - # Render footer. - # Values: True, False (Default: True) - 'show_footer': True, + 'globaltoc_depth': 4, # Hide the symbiflow links 'hide_symbiflow_links': True, From 3431f934a972fe46b5b6e893681a25950e877ca4 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 1 Nov 2021 09:56:56 -0700 Subject: [PATCH 23/40] Small tweaks to documentation configuration. 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For a list of options available for each theme, see the # documentation. # https://sphinx-symbiflow-theme.readthedocs.io/en/latest/customization.html html_theme_options = { + 'nav_title': 'SkyWater SKY130 PDK', + 'color_primary': 'light-green', 'color_accent': 'teal', From 1a47a4f774ff46bb354de418f38c215fba4ebc1f Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 1 Nov 2021 11:52:11 -0700 Subject: [PATCH 24/40] Adding more top level links. Signed-off-by: Tim 'mithro' Ansell --- docs/_templates/relbar.html | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 docs/_templates/relbar.html diff --git a/docs/_templates/relbar.html b/docs/_templates/relbar.html new file mode 100644 index 0000000..d693e3e --- /dev/null +++ b/docs/_templates/relbar.html @@ -0,0 +1,13 @@ +{% extends '!relbar.html' %} + +{%- block extralinks -%} +{{ super() }} + +
  • business SkyWater
    • +
  • precision_manufacturing Shuttle Program
    • +
  • chat_bubble Chat
    • +
  • campaignAnnouncements
    • +
  • mail Mailing List
    • + + +{%- endblock -%} From b57bd58ad260561c65715e3ec9d25861f2929074 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 2 Nov 2021 08:09:17 -0700 Subject: [PATCH 25/40] docs: Remove unneeded comment in Sphinx config. Signed-off-by: Tim 'mithro' Ansell --- docs/conf.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index 69d4165..7bcac17 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -165,12 +165,6 @@ html_theme_options = { 'github_url': 'https://github.com/google/skywater-pdk', 'repo_name': 'google/skywater-pdk', -# 'nav_links': [ -# ('Home', 'index', False, 'home'), -# ("GitHub", "https://github.com/google/skywater-pdk", True, 'code'), -# ("SkyWater", "https://www.skywatertechnology.com/", True, 'link'), -# ], - 'globaltoc_depth': 4, # Hide the symbiflow links From 73e9c8402d7fa125cecc5e7a8d7a4e80faa16a34 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 2 Nov 2021 08:19:20 -0700 Subject: [PATCH 26/40] docs: Include toc in sidebar. Signed-off-by: Tim 'mithro' Ansell --- docs/conf.py | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/conf.py b/docs/conf.py index 7bcac17..36ba1bb 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -166,6 +166,7 @@ html_theme_options = { 'repo_name': 'google/skywater-pdk', 'globaltoc_depth': 4, + 'globaltoc_collapse': False, # Hide the symbiflow links 'hide_symbiflow_links': True, From 68a2c36bb512eebec088ae8be29902e37b8dc907 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Wed, 24 Nov 2021 13:18:46 -0800 Subject: [PATCH 27/40] Adding ReRAM PDK to the submodules directory of the skywater repo Signed-off-by: Ethan Mahintorabi --- .gitmodules | 30 ++++++++++++++++++++++++++++- libraries/sky130_fd_pr_reram/latest | 1 + libraries/sky130_fd_pr_reram/v0.0.9 | 1 + libraries/sky130_fd_pr_reram/v2.0.1 | 1 + libraries/sky130_fd_pr_reram/v2.0.2 | 1 + libraries/sky130_fd_pr_reram/v2.0.3 | 1 + 6 files changed, 34 insertions(+), 1 deletion(-) create mode 160000 libraries/sky130_fd_pr_reram/latest create mode 160000 libraries/sky130_fd_pr_reram/v0.0.9 create mode 160000 libraries/sky130_fd_pr_reram/v2.0.1 create mode 160000 libraries/sky130_fd_pr_reram/v2.0.2 create mode 160000 libraries/sky130_fd_pr_reram/v2.0.3 diff --git a/.gitmodules b/.gitmodules index 0874f66..464b6c4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -160,7 +160,6 @@ branch = branch-0.1.0 shallow = true fetchRecurseSubmodules = false - # sky130_fd_sc_lp [submodule "libraries/sky130_fd_sc_lp/latest"] path = libraries/sky130_fd_sc_lp/latest @@ -244,3 +243,32 @@ branch = branch-0.0.1 shallow = true fetchRecurseSubmodules = false +#sky130_fd_pr_reram +[submodule "libraries/sky130_fd_pr_reram/v0.0.9"] + path = libraries/sky130_fd_pr_reram/v0.0.9 + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git + branch = branch-0.0.9 + shallow = true + fetchRecurseSubmodules = false +[submodule "libraries/sky130_fd_pr_reram/v2.0.1"] + path = libraries/sky130_fd_pr_reram/v2.0.1 + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git + branch = branch-2.0.1 + shallow = true + fetchRecurseSubmodules = false +[submodule "libraries/sky130_fd_pr_reram/v2.0.2"] + path = libraries/sky130_fd_pr_reram/v2.0.2 + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git + branch = branch-2.0.2 + shallow = true + fetchRecurseSubmodules = false +[submodule "libraries/sky130_fd_pr_reram/v2.0.3"] + path = libraries/sky130_fd_pr_reram/v2.0.3 + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git + branch = branch-2.0.3 + shallow = true + fetchRecurseSubmodules = false +[submodule "libraries/sky130_fd_pr_reram/latest"] + path = libraries/sky130_fd_pr_reram/latest + url = https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram.git + branch = main diff --git a/libraries/sky130_fd_pr_reram/latest b/libraries/sky130_fd_pr_reram/latest new file mode 160000 index 0000000..48c8310 --- /dev/null +++ b/libraries/sky130_fd_pr_reram/latest @@ -0,0 +1 @@ +Subproject commit 48c8310e464157d797c78cb2e6d6b5a21d710c20 diff --git a/libraries/sky130_fd_pr_reram/v0.0.9 b/libraries/sky130_fd_pr_reram/v0.0.9 new file mode 160000 index 0000000..1ed5750 --- /dev/null +++ b/libraries/sky130_fd_pr_reram/v0.0.9 @@ -0,0 +1 @@ +Subproject commit 1ed57501be4b8b7816942b7eac6f864910025799 diff --git a/libraries/sky130_fd_pr_reram/v2.0.1 b/libraries/sky130_fd_pr_reram/v2.0.1 new file mode 160000 index 0000000..21212f5 --- /dev/null +++ b/libraries/sky130_fd_pr_reram/v2.0.1 @@ -0,0 +1 @@ +Subproject commit 21212f530de3b071e4737a7622ce3c7dce1527bb diff --git a/libraries/sky130_fd_pr_reram/v2.0.2 b/libraries/sky130_fd_pr_reram/v2.0.2 new file mode 160000 index 0000000..ef3ec3e --- /dev/null +++ b/libraries/sky130_fd_pr_reram/v2.0.2 @@ -0,0 +1 @@ +Subproject commit ef3ec3edd3d30a35ff04011fd3afc8f2cdd1d06f diff --git a/libraries/sky130_fd_pr_reram/v2.0.3 b/libraries/sky130_fd_pr_reram/v2.0.3 new file mode 160000 index 0000000..d3c4505 --- /dev/null +++ b/libraries/sky130_fd_pr_reram/v2.0.3 @@ -0,0 +1 @@ +Subproject commit d3c4505de8ec4c52fe70c276b351929297ffcd6e From 5d0ba2fb8bfb10fb1db630644d03474c466827b2 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Tue, 19 Apr 2022 19:42:47 +0200 Subject: [PATCH 28/40] docs/environment: do not require yosys Signed-off-by: Unai Martinez-Corral --- docs/environment.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/environment.yml b/docs/environment.yml index 7100f6f..d8345d8 100644 --- a/docs/environment.yml +++ b/docs/environment.yml @@ -20,7 +20,6 @@ channels: dependencies: - python=3.8 - pip -- yosys - netlistsvg # Packages installed from PyPI - pip: From 1c598bd0571b3513886cd2c37ddd8dd3f63d4330 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 21 Apr 2022 14:29:27 +0000 Subject: [PATCH 29/40] build(deps): Bump crazy-max/ghaction-github-labeler from 3.1.0 to 3.1.1 Bumps [crazy-max/ghaction-github-labeler](https://github.com/crazy-max/ghaction-github-labeler) from 3.1.0 to 3.1.1. - [Release notes](https://github.com/crazy-max/ghaction-github-labeler/releases) - [Changelog](https://github.com/crazy-max/ghaction-github-labeler/blob/master/CHANGELOG.md) - [Commits](https://github.com/crazy-max/ghaction-github-labeler/compare/v3.1.0...v3.1.1) Signed-off-by: dependabot[bot] --- .github/workflows/manage-labels.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/manage-labels.yml b/.github/workflows/manage-labels.yml index 35b6777..887c329 100644 --- a/.github/workflows/manage-labels.yml +++ b/.github/workflows/manage-labels.yml @@ -12,7 +12,7 @@ jobs: - name: Run Labeler if: success() - uses: crazy-max/ghaction-github-labeler@v3.1.0 + uses: crazy-max/ghaction-github-labeler@v3.1.1 with: yaml_file: .github/labels.yml env: From 66f65cd57d35a10828d2181e415dba876ed2e8f7 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Thu, 21 Apr 2022 14:29:51 +0000 Subject: [PATCH 30/40] build(deps): Bump actions/checkout from 2 to 3 Bumps [actions/checkout](https://github.com/actions/checkout) from 2 to 3. - [Release notes](https://github.com/actions/checkout/releases) - [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md) - [Commits](https://github.com/actions/checkout/compare/v2...v3) --- updated-dependencies: - dependency-name: actions/checkout dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/manage-labels.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/manage-labels.yml b/.github/workflows/manage-labels.yml index 35b6777..2376bff 100644 --- a/.github/workflows/manage-labels.yml +++ b/.github/workflows/manage-labels.yml @@ -8,7 +8,7 @@ jobs: steps: - name: Checkout - uses: actions/checkout@v2 + uses: actions/checkout@v3 - name: Run Labeler if: success() From dee9f428634e43eba619a2edb672e97e278f34d5 Mon Sep 17 00:00:00 2001 From: Johan Euphrosine Date: Fri, 1 Jul 2022 16:01:31 +0900 Subject: [PATCH 31/40] github/labels: add ngspice --- .github/labels.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/labels.yml b/.github/labels.yml index 30c8c0f..6f32df8 100644 --- a/.github/labels.yml +++ b/.github/labels.yml @@ -241,6 +241,10 @@ description: "Issues with using OpenROAD with the PDK." color: "054caa" +- name: "tools-ngspice" + description: "Issues with using Ngspice with the PDK." + color: "054caa" + # Partially open or with closed source dependencies. - name: "tools-BAG" description: "Issues with using the Berkeley Analog Generator (BAG) with the PDK." From 51f4771c3894b7b417837dbec0021749a01a75c7 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 1 Jul 2022 07:35:50 +0000 Subject: [PATCH 32/40] build(deps): Bump crazy-max/ghaction-github-labeler from 3.1.1 to 4.0.0 Bumps [crazy-max/ghaction-github-labeler](https://github.com/crazy-max/ghaction-github-labeler) from 3.1.1 to 4.0.0. - [Release notes](https://github.com/crazy-max/ghaction-github-labeler/releases) - [Changelog](https://github.com/crazy-max/ghaction-github-labeler/blob/master/CHANGELOG.md) - [Commits](https://github.com/crazy-max/ghaction-github-labeler/compare/v3.1.1...v4.0.0) --- updated-dependencies: - dependency-name: crazy-max/ghaction-github-labeler dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/manage-labels.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/manage-labels.yml b/.github/workflows/manage-labels.yml index c9e3c80..838c2c0 100644 --- a/.github/workflows/manage-labels.yml +++ b/.github/workflows/manage-labels.yml @@ -12,7 +12,7 @@ jobs: - name: Run Labeler if: success() - uses: crazy-max/ghaction-github-labeler@v3.1.1 + uses: crazy-max/ghaction-github-labeler@v4.0.0 with: yaml_file: .github/labels.yml env: From 99274f31eb79614e3b8ee2027071cb4d3ad4e6f5 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 12 Jul 2022 16:59:42 -0700 Subject: [PATCH 33/40] Fixing Sphinx config for GitHub. Signed-off-by: Tim 'mithro' Ansell --- docs/conf.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index 36ba1bb..ba4b171 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -86,8 +86,8 @@ if not on_rtd: "display_github": True, # Integrate GitHub "github_user": "google", # Username "github_repo": "skywater-pdk", # Repo name - "github_version": "master", # Version - "conf_py_path": "/doc/", + "github_version": "main", # Version + "conf_py_path": "/docs/", } else: docs_dir = os.path.abspath(os.path.dirname(__file__)) From e0fc892c1c240fce20a3457eebb22ccf697b2a46 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 12 Jul 2022 19:27:38 -0700 Subject: [PATCH 34/40] Fixing the announcement link in top level bar. Signed-off-by: Tim 'mithro' Ansell --- docs/_templates/relbar.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/_templates/relbar.html b/docs/_templates/relbar.html index d693e3e..a61838b 100644 --- a/docs/_templates/relbar.html +++ b/docs/_templates/relbar.html @@ -6,7 +6,7 @@
  • business SkyWater
  • precision_manufacturing Shuttle Program
  • chat_bubble Chat
    • -
  • campaignAnnouncements
    • +
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    • From e06e29c9547ccf1d6159a91ea2556768608cca6e Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Tue, 26 Apr 2022 01:40:59 +0200 Subject: [PATCH 35/40] docs: add References through BibTeX Signed-off-by: Unai Martinez-Corral --- docs/conf.py | 4 ++++ docs/index.rst | 2 +- docs/references.rst | 8 ++++++++ docs/refs.bib | 6 ++++++ docs/requirements.txt | 1 + 5 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 docs/references.rst create mode 100644 docs/refs.bib diff --git a/docs/conf.py b/docs/conf.py index ba4b171..77aadb4 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -65,8 +65,12 @@ extensions = [ 'sphinx.ext.napoleon', 'sphinx.ext.todo', 'sphinxcontrib_hdl_diagrams', + 'sphinxcontrib.bibtex', ] +bibtex_default_style = 'plain' +bibtex_bibfiles = ['refs.bib'] + # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] diff --git a/docs/index.rst b/docs/index.rst index 828ea9b..3261a63 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -24,7 +24,7 @@ contributing partners - + references Welcome to SkyWater SKY130 PDK's documentation! diff --git a/docs/references.rst b/docs/references.rst new file mode 100644 index 0000000..4563312 --- /dev/null +++ b/docs/references.rst @@ -0,0 +1,8 @@ +.. _References: + +References +########## + +.. bibliography:: + :notcited: + :labelprefix: R diff --git a/docs/refs.bib b/docs/refs.bib new file mode 100644 index 0000000..5d605d1 --- /dev/null +++ b/docs/refs.bib @@ -0,0 +1,6 @@ +@Online{SkyWaterPDKIntro_Edwards21, + author = {Edwards, Tim}, + title = {{Introduction to the SkyWater PDK: The New Age of Open Source Silicon}}, + url = {https://isn.ucsd.edu/courses/beng207/lectures/Tim_Edwards_2021_slides.pdf}, + year = {2021}, +} diff --git a/docs/requirements.txt b/docs/requirements.txt index 056d192..4605163 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -3,6 +3,7 @@ git+https://github.com/SymbiFlow/sphinx_symbiflow_theme.git#egg=sphinx-symbiflow docutils sphinx sphinx-autobuild +sphinxcontrib-bibtex # Verilog domain sphinx-verilog-domain From 201bedc59e318875f06da5013ba040b59a1bd8b3 Mon Sep 17 00:00:00 2001 From: Balint Cristian Date: Thu, 6 Oct 2022 15:41:00 +0300 Subject: [PATCH 36/40] Enable additional PDF output for readthedocs.io --- .readthedocs.yml | 3 +++ docs/conf.py | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/.readthedocs.yml b/.readthedocs.yml index 5321847..bea9451 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -32,3 +32,6 @@ submodules: include: - libraries/sky130_fd_io/latest recursive: false + +formats: + - pdf diff --git a/docs/conf.py b/docs/conf.py index 77aadb4..f5c16d7 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -61,6 +61,7 @@ extensions = [ 'sphinx.ext.autosectionlabel', 'sphinx.ext.githubpages', 'sphinx.ext.ifconfig', + 'sphinx.ext.imgconverter', 'sphinx.ext.mathjax', 'sphinx.ext.napoleon', 'sphinx.ext.todo', @@ -295,6 +296,23 @@ numfig = True # If true, `todo` and `todoList` produce output, else they produce nothing. todo_include_todos = True +latex_elements = { + 'preamble': r'\DeclareUnicodeCharacter{03A9}{\ensuremath{\Omega}}' + + r'\DeclareUnicodeCharacter{03BC}{\ensuremath{\mu}}' + + r'\DeclareUnicodeCharacter{2184}{\ensuremath{\supset}}' + + r'\DeclareUnicodeCharacter{2295}{\ensuremath{\oplus}}' + + r'\DeclareUnicodeCharacter{2228}{\ensuremath{\vee}}' + + r'\DeclareUnicodeCharacter{22BB}{\ensuremath{\veebar}}' + + r'\DeclareUnicodeCharacter{01C1}{\ensuremath{\parallel}}' + + r'\DeclareUnicodeCharacter{2220}{\ensuremath{\angle}}' + + r'\DeclareUnicodeCharacter{2227}{\ensuremath{\wedge}}' + + r'\DeclareUnicodeCharacter{25A1}{\ensuremath{\Box}}' + + r'\DeclareUnicodeCharacter{F06D}{\ensuremath{\mu}}' + + r'\DeclareUnicodeCharacter{03B2}{\ensuremath{\beta}}' + + r'\DeclareUnicodeCharacter{2264}{\ensuremath{\leq}}' + + r'\usepackage{pmboxdraw}' + + r'\DeclareUnicodeCharacter{2534}{\textSFvii}' +} import re from docutils.parsers.rst import directives, roles, nodes From d1d38dffee18919cd1dc23e6cc5b6c427992e816 Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 31 Oct 2022 20:17:21 +0100 Subject: [PATCH 37/40] reorder device detail sections --- docs/rules/device-details.py | 67 +- docs/rules/device-details.rst | 1422 +++++++++---------- docs/rules/device-details/cap_var/index.rst | 4 +- 3 files changed, 765 insertions(+), 728 deletions(-) diff --git a/docs/rules/device-details.py b/docs/rules/device-details.py index ce51e73..2a84c79 100755 --- a/docs/rules/device-details.py +++ b/docs/rules/device-details.py @@ -2,28 +2,66 @@ import re import os -import sys -from pathlib import Path -from pprint import pformat - RE_IMAGE = re.compile('.. (.*) image:: (.*)') RE_INCLUDE = re.compile('.. include:: (.*)') +device_list = [ + # 1.8V MOS + "nfet_01v8", + "nfet_01v8_lvt", + "pfet_01v8", + "pfet_01v8_lvt", + "pfet_01v8_hvt", + "cap_var", + + # 3.3V MOS + "nfet_03v3_nvt", + + # 5V MOS + "nfet_05v0_nvt", + "nfet_g5v0d10v5", + "pfet_g5v0d10v5", + "pfet_g5v0d16v0", + + # 11V MOS + "nfet_g11v0d16v0", + + # 20V MOS + "nfet_20v0", + "nfet_20v0_iso", + "nfet_20v0_nvt", + "nfet_20v0_zvt", + "pfet_20v0", + + # ESD MOS + "esd_nfet", + + # Diodes/Bipolar + "diodes", + "npn_05v0", + "pnp_05v0", + + # Special active devices + "special_sram", + "special_sonosfet", + + # Well/Diffusion/Poly/Metal Resistors + "res_generic", + "res_high", + "res_xhigh", + + # Metal Capacitors + "cap_mim", + "cap_vpp", +] + print('Device Details') print('==============') print() -def r(m): - n = m.group(0) - while len(n) < 10: - n = '0'+n - return n - -def k(s): - return re.sub('([0-9.V/]*)', r, str(s)) - -for fname in sorted(Path('.').rglob('index.rst'), key=k): +for device_name in device_list: + fname = os.path.join("device-details", device_name, "index.rst") with open(fname) as f: data = f.read() @@ -33,4 +71,3 @@ for fname in sorted(Path('.').rglob('index.rst'), key=k): data = RE_IMAGE.sub(r'.. \1 image:: {}/\2'.format(dirname), data) data = RE_INCLUDE.sub(r'.. include:: {}/\1'.format(dirname), data) print(data) - diff --git a/docs/rules/device-details.rst b/docs/rules/device-details.rst index 6ae9877..2997b36 100644 --- a/docs/rules/device-details.rst +++ b/docs/rules/device-details.rst @@ -1,371 +1,43 @@ Device Details ============== -MiM Capacitor +1.8V NMOS FET ------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ -- Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base` -- Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4` - -Operating Voltages where SPICE models are valid - -- :math:`|V_{c0} – V_{c1}| = 0` to 5.0V - -Details -~~~~~~~ - -The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions: - -- CAPM over Metal-3 -- CAP2M over Metal-4 - -The constructions are identical, and the capacitors may be stacked to maximize total capacitance. - -Electrical specs are listed below: - - -.. include:: device-details/cap_mim/cap_mim-table0.rst - - - -The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate. - -|symbol-cap_mim| - -Cell name - -M \* W \* L - -Calc capacitance - -The cross-section of the “stacked” MiM capacitor is shown below: - -|cross-section-cap_mim| - -.. |symbol-cap_mim| image:: device-details/cap_mim/symbol-cap_mim.svg -.. |cross-section-cap_mim| image:: device-details/cap_mim/cross-section-cap_mim.svg - - -Varactors ---------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`capbn_b` -- Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt` -- Model Type: subcircuit - -Operating Voltages where SPICE models are valid - -- :math:`|V_0 – V_1| = 0` to 2.0V - -Details -~~~~~~~ - -The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model: - -- :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option -- :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option - -The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request. - - -.. include:: device-details/cap_var/cap_var-table0.rst - - - -There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V. - -The symbols for the varactors are shown below: - -|symbol-cap_var-a| |symbol-cap_var-b| - -The cross-section of the varactor is shown below: - -|cross-section-cap_var| - -.. |symbol-cap_var-a| image:: device-details/cap_var/symbol-cap_var-a.svg -.. |symbol-cap_var-b| image:: device-details/cap_var/symbol-cap_var-b.svg -.. |cross-section-cap_var| image:: device-details/cap_var/cross-section-cap_var.svg - - -Vertical Parallel Plate (VPP) capacitors ----------------------------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))` -- Model Names: :model:`sky130_fd_pr__cap_vpp_*` - - - X and Y are size dimentions - - MM refers to the layers which are used for the capacitance - - SS refers to the layers which are used as shields (`noshield` when no shield is used) - - FF refers to the layers which are floating. - - VVVVV refers to the "variant" when there are multiple devices of the same configuration - -Operating Voltages where SPICE models are valid - -- :math:`|V_{c0} – V_{c1}| = 0` to 5.5V - -Details -~~~~~~~ - -The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below: - -.. todo:: - - M3 - - **M2** - - LI - - M1 - - LAYOUT of M2, M3, M4 - - LAYOUT of LI and M1 (with POLY sheet) - - **POLY** - - **M4** - -These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions. - -Parallel VPP Capacitors -^^^^^^^^^^^^^^^^^^^^^^^ - -These are older versions, where stacked metal lines run parallel: - - -- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield` (M1 \|\| M2 only, 7.84 x 8.58) -- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2` (M1 \|\| M2 only, 4.38 x 4.59) -- :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield` (M1 \|\| M2 only, 2.19 x 4.59) -- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield` (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants) -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield` (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants) -- :model:`sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield` -- :model:`sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0) -- :model:`sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2` (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0) -- :model:`sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0) -- :model:`sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0) -- :model:`sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0) - -The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well). - -|symbol-cap_vpp-parallel| - -Perpendicular VPP Capacitors -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom: - -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5` (11.5x11.7, with M5 shield) -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5` (11.5x11.7, with poly and M5 shield) -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5` (11.5x11.7, with LI and M5 shield) -- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4` (4.4x4.6, M3 float, LI / M5 shield) -- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4` (8.6x7.9, M3 float, LI / M5 shield) -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4` (11.5x11.7, M3 float, LI / M5 shield) -- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4` (11.5x11.7, with M4 shield) -- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4` (6.8x6.1, with poly and M4 shield) -- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4` (6.8x6.1, with LI and M4 shield) -- :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5` (11.5x11.7, over 2 :model:`sky130_fd_pr__nfet_05v0_nvt` of 10/4 each) - -The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield. - -|symbol-cap_vpp-perpendicular| - -The capacitors are fixed-size elements and must be used as-is; they can be used in multiples. - - -.. include:: device-details/cap_vpp/cap_vpp-table0.rst - -.. |symbol-cap_vpp-parallel| image:: device-details/cap_vpp/symbol-cap_vpp-parallel.svg -.. |symbol-cap_vpp-perpendicular| image:: device-details/cap_vpp/symbol-cap_vpp-perpendicular.svg - -Diodes ------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`diode` -- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pw2nd_05v5_nvt`, :model:`sky130_fd_pr__diode_pw2nd_05v5_lvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5_hvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5_lvt`, :model:`sky130_fd_pr__model__parasitic__rf_diode_ps2nw`, :model:`sky130_fd_pr__model__parasitic__rf_diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`sky130_fd_pr__model__parasitic__diode_ps2nw`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)` -- Cell Name: :cell:`lvsdiode` -- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)` - -Operating regime where SPICE models are valid - -- :math:`|V_{d0} – V_{d1}| = 0` to 5.0V - -Details -~~~~~~~ - - -.. include:: device-details/diodes/diodes-table0.rst - - - -Symbols for the diodes are shown below - -|symbol-diode-01| -|symbol-diode-02| -|symbol-diode-03| -|symbol-diode-04| -|symbol-diode-05| -|symbol-diode-06| -|symbol-diode-07| -|symbol-diode-08| -|symbol-diode-09| -|symbol-diode-10| -|symbol-diode-11| -|symbol-diode-12| -|symbol-diode-13| -|symbol-diode-14| -|symbol-diode-15| -|symbol-diode-16| -|symbol-diode-17| - -.. |symbol-diode-01| image:: device-details/diodes/symbol-diode-01.svg -.. |symbol-diode-02| image:: device-details/diodes/symbol-diode-02.svg -.. |symbol-diode-03| image:: device-details/diodes/symbol-diode-03.svg -.. |symbol-diode-04| image:: device-details/diodes/symbol-diode-04.svg -.. |symbol-diode-05| image:: device-details/diodes/symbol-diode-05.svg -.. |symbol-diode-06| image:: device-details/diodes/symbol-diode-06.svg -.. |symbol-diode-07| image:: device-details/diodes/symbol-diode-07.svg -.. |symbol-diode-08| image:: device-details/diodes/symbol-diode-08.svg -.. |symbol-diode-09| image:: device-details/diodes/symbol-diode-09.svg -.. |symbol-diode-10| image:: device-details/diodes/symbol-diode-10.svg -.. |symbol-diode-11| image:: device-details/diodes/symbol-diode-11.svg -.. |symbol-diode-12| image:: device-details/diodes/symbol-diode-12.svg -.. |symbol-diode-13| image:: device-details/diodes/symbol-diode-13.svg -.. |symbol-diode-14| image:: device-details/diodes/symbol-diode-14.svg -.. |symbol-diode-15| image:: device-details/diodes/symbol-diode-15.svg -.. |symbol-diode-16| image:: device-details/diodes/symbol-diode-16.svg -.. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg - - -NMOS ESD FET ------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - - Cell Name: :cell:`sky130_fd_pr__nfet_01v8` -- Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` +- Model Name: :model:`sky130_fd_pr__nfet_01v8` Operating Voltages where SPICE models are valid -- :math:`V_{DS} = 0` to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) -- :math:`V_{GS} = 0` to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) -- :math:`V_{BS} = 0` to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`) +- :math:`V_{DS} = 0` to 1.95V +- :math:`V_{GS} = 0` to 1.95V +- :math:`V_{BS} = +0.3` to -1.95V Details ~~~~~~~ -The ESD FET’s differ from the regular NMOS devices in several aspects, most notably: - -- Increased isolation spacing from contacts to surrounding STI -- Increased drain contact-to-gate spacing -- Placement of n-well under the drain contacts - -Major model output parameters are shown below and compared against the EDR (e-test) specs +Major model output parameters are shown below and compared against the EDR (e-test) specs. -.. include:: device-details/esd_nfet/esd_nfet-table0.rst +.. include:: device-details/nfet_01v8/nfet_01v8-table0.rst -The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below: +The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below: -|symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt| +|symbol-nfet_01v8| -The cross-section of the ESD NMOS FET is shown below. +The cross-section of the NMOS FET is shown below: -|cross-section-esd_nfet| +|cross-section-nfet_01v8| -.. |symbol-esd_nfet_g5v0d10v5| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5.svg -.. |symbol-esd_nfet_g5v0d10v5_nvt| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5_nvt.svg -.. |cross-section-esd_nfet| image:: device-details/esd_nfet/cross-section-esd_nfet.svg +The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well - -5.0V/10.5V NMOS FET -------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` -- Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5` - -Operating Voltages where SPICE models are valid - -- :math:`V_{DS} = 0` to 11.0V -- :math:`V_{GS} = 0` to 5.5V -- :math:`V_{BS} = 0` to -5.5V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/nfet_g5v0d10v5/nfet_g5v0d10v5-table0.rst - - - -The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below: - -|symbol-nfet_g5v0d10v5| - -The cross-section of the 5.0/10.5 V NMOS FET is shown below. - -|cross-section-nfet_g5v0d10v5| - -.. |symbol-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/symbol-nfet_g5v0d10v5.svg -.. |cross-section-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/cross-section-nfet_g5v0d10v5.svg - - -11V/16V NMOS FET ----------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` -- Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0` - -Operating Voltages where SPICE models are valid, subject to SOA limitations: - -- :math:`V_{DS} = 0` to +16V (\ :math:`V_{GS} = 0`\ ) -- :math:`V_{DS} = 0` to +11V (\ :math:`V_{GS} > 0`\ ) -- :math:`V_{GS} = 0` to 5.5V -- :math:`V_{BS} = 0` to -2.0V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/nfet_g11v0d16v0/nfet_g11v0d16v0-table0.rst - - - -The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below: - -|symbol-nfet_g11v0d16v0| - -The cross-section of the 11V/16VV NMOS FET is shown below. - -|cross-section-nfet_g11v0d16v0| - -.. |symbol-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/symbol-nfet_g11v0d16v0.svg -.. |cross-section-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/cross-section-nfet_g11v0d16v0.svg +.. |symbol-nfet_01v8| image:: device-details/nfet_01v8/symbol-nfet_01v8.svg +.. |cross-section-nfet_01v8| image:: device-details/nfet_01v8/cross-section-nfet_01v8.svg 1.8V low-VT NMOS FET @@ -412,20 +84,20 @@ The cross-section of the low-VT NMOS FET is shown below. The cross-section is id .. |cross-section-nfet_01v8_lvt| image:: device-details/nfet_01v8_lvt/cross-section-nfet_01v8_lvt.svg -1.8V NMOS FET +1.8V PMOS FET ------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` -- Model Name: :model:`sky130_fd_pr__nfet_01v8` +- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` +- Model Name: :model:`sky130_fd_pr__pfet_01v8` Operating Voltages where SPICE models are valid -- :math:`V_{DS} = 0` to 1.95V -- :math:`V_{GS} = 0` to 1.95V -- :math:`V_{BS} = +0.3` to -1.95V +- :math:`V_{DS} = 0` to -1.95V +- :math:`V_{GS} = 0` to -1.95V +- :math:`V_{BS} = -0.1` to +1.95V Details ~~~~~~~ @@ -433,22 +105,159 @@ Details Major model output parameters are shown below and compared against the EDR (e-test) specs. -.. include:: device-details/nfet_01v8/nfet_01v8-table0.rst +.. include:: device-details/pfet_01v8/pfet_01v8-table0.rst -The symbol of the :model:`sky130_fd_pr__nfet_01v8` (1.8V NMOS FET) is shown below: +Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations: -|symbol-nfet_01v8| -The cross-section of the NMOS FET is shown below: +.. include:: device-details/pfet_01v8/pfet_01v8-table1.rst -|cross-section-nfet_01v8| -The device shows the p-well inside of a deep n-well, but it can be made either with or without the DNW under the p-well -.. |symbol-nfet_01v8| image:: device-details/nfet_01v8/symbol-nfet_01v8.svg -.. |cross-section-nfet_01v8| image:: device-details/nfet_01v8/cross-section-nfet_01v8.svg +The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below: + +|symbol-pfet_01v8| + +The cross-section of the PMOS FET is shown below: + +|cross-section-pfet_01v8| + +.. |symbol-pfet_01v8| image:: device-details/pfet_01v8/symbol-pfet_01v8.svg +.. |cross-section-pfet_01v8| image:: device-details/pfet_01v8/cross-section-pfet_01v8.svg + + +1.8V low-VT PMOS FET +-------------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` +- Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt` + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to -1.95V +- :math:`V_{GS} = 0` to -1.95V +- :math:`V_{BS} = -0.1` to +1.95V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table0.rst + + + +Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations: + + +.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table1.rst + + + +The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below: + +|symbol-pfet_01v8_lvt| + +The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`) + +|cross-section-pfet_01v8_lvt| + +.. |symbol-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/symbol-pfet_01v8_lvt.svg +.. |cross-section-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/cross-section-pfet_01v8_lvt.svg + + +1.8V high-VT PMOS FET +--------------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` +- Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt` + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to -1.95V +- :math:`V_{GS} = 0` to -1.95V +- :math:`V_{BS} = -0.1` to +1.95V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table0.rst + + + +Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations: + + +.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table1.rst + + + +The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below: + +|symbol-pfet_01v8_hvt| + +The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the higher :math:`V_T`) + +|cross-section-pfet_01v8_hvt| + +.. |symbol-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/symbol-pfet_01v8_hvt.svg +.. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg + + +1.8V Accumulation-Mode MOS Varactors +------------------------------------ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`capbn_b` +- Model Name: :model:`sky130_fd_pr__cap_var_lvt`, :model:`sky130_fd_pr__cap_var_hvt` +- Model Type: subcircuit + +Operating Voltages where SPICE models are valid + +- :math:`|V_0 – V_1| = 0` to 2.0V + +Details +~~~~~~~ + +The following devices are available; they are subcircuits with the N-well to P-substrate diodes built into the model: + +- :model:`sky130_fd_pr__cap_var_lvt` - low VT PMOS device option +- :model:`sky130_fd_pr__cap_var_hvt` - high VT PMOS device option + +The varactors are used as tunable capacitors, major e-test parameters are listed below. Further details on the device models and their usage are in the SKY130 process Family Spice Models (002-21997), which can be obtained from SkyWater upon request. + + +.. include:: device-details/cap_var/cap_var-table0.rst + + + +There is no equivalent varactor for 5V operation. The NHV or PHV devices should be connected as capacitors for use at 5V. + +The symbols for the varactors are shown below: + +|symbol-cap_var-a| |symbol-cap_var-b| + +The cross-section of the varactor is shown below: + +|cross-section-cap_var| + +.. |symbol-cap_var-a| image:: device-details/cap_var/symbol-cap_var-a.svg +.. |symbol-cap_var-b| image:: device-details/cap_var/symbol-cap_var-b.svg +.. |cross-section-cap_var| image:: device-details/cap_var/cross-section-cap_var.svg 3.0V native NMOS FET @@ -498,7 +307,7 @@ The cross-section of the native devices is shown below. Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Cell Name: :cell:`sky130_fd_pr__nfet_05v0_nvt` - Model Name: :model:`sky130_fd_pr__nfet_05v0_nvt` Operating Voltages where SPICE models are valid for :model:`sky130_fd_pr__nfet_05v0_nvt` @@ -534,6 +343,164 @@ The cross-section of the native devices is shown below. .. |cross-section-nfet_05v0_nvt| image:: device-details/nfet_05v0_nvt/../nfet_03v3_nvt-and-nfet_05v0_nvt/cross-section-nfet_03v3_nvt-and-nfet_05v0_nvt.svg +5.0V/10.5V NMOS FET +------------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Model Name: :model:`sky130_fd_pr__nfet_g5v0d10v5` + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to 11.0V +- :math:`V_{GS} = 0` to 5.5V +- :math:`V_{BS} = 0` to -5.5V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/nfet_g5v0d10v5/nfet_g5v0d10v5-table0.rst + + + +The symbols of the :model:`sky130_fd_pr__nfet_g5v0d10v5` (5.0/10.5 V NMOS FET) is shown below: + +|symbol-nfet_g5v0d10v5| + +The cross-section of the 5.0/10.5 V NMOS FET is shown below. + +|cross-section-nfet_g5v0d10v5| + +.. |symbol-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/symbol-nfet_g5v0d10v5.svg +.. |cross-section-nfet_g5v0d10v5| image:: device-details/nfet_g5v0d10v5/cross-section-nfet_g5v0d10v5.svg + + +5.0V/10.5V PMOS FET +------------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` +- Model Name: :model:`sky130_fd_pr__pfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to -11.0V +- :math:`V_{GS} = 0` to -5.5V +- :math:`V_{BS} = 0` to +5.5V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table0.rst + + + +Inverter gate delays are shown below: + + +.. include:: device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table1.rst + + + +The symbols of the :model:`sky130_fd_pr__pfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` (5.0V/10.5V PMOS FET) are shown below: + +|symbol-pfet_g5v0d10v5| |symbol-esd_pfet_g5v0d10v5| + +The cross-section of the 5.0V PMOS FET is shown below. + +|cross-section-pfet_g5v0d10v5| + +.. |symbol-pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/symbol-pfet_g5v0d10v5.svg +.. |symbol-esd_pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/symbol-esd_pfet_g5v0d10v5.svg +.. |cross-section-pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/cross-section-pfet_g5v0d10v5.svg + + +10V/16V PMOS FET +---------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` +- Model Name: :model:`sky130_fd_pr__pfet_g5v0d16v0` + +Operating Voltages where SPICE models are valid, subject to SOA limitations: + +- :math:`V_{DS} = 0` to -16V (\ :math:`V_{GS} = 0`\ ) +- :math:`V_{DS} = 0` to -10V (\ :math:`V_{GS} < 0`\ ) +- :math:`V_{GS} = 0` to -5.5V +- :math:`V_{BS} = 0` to +2.0V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/pfet_g5v0d16v0/pfet_g5v0d16v0-table0.rst + + + +The symbol of the :model:`sky130_fd_pr__pfet_g5v0d16v0` (10V/16V PMOS FET) is shown below: + +|symbol-pfet_g5v0d16v0| + +The cross-section of the 10V/16V PMOS FET is shown below. + +|cross-section-pfet_g5v0d16v0| + +.. |symbol-pfet_g5v0d16v0| image:: device-details/pfet_g5v0d16v0/symbol-pfet_g5v0d16v0.svg +.. |cross-section-pfet_g5v0d16v0| image:: device-details/pfet_g5v0d16v0/cross-section-pfet_g5v0d16v0.svg + + +11V/16V NMOS FET +---------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` +- Model Name: :model:`sky130_fd_pr__nfet_g5v0d16v0` + +Operating Voltages where SPICE models are valid, subject to SOA limitations: + +- :math:`V_{DS} = 0` to +16V (\ :math:`V_{GS} = 0`\ ) +- :math:`V_{DS} = 0` to +11V (\ :math:`V_{GS} > 0`\ ) +- :math:`V_{GS} = 0` to 5.5V +- :math:`V_{BS} = 0` to -2.0V + +Details +~~~~~~~ + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/nfet_g11v0d16v0/nfet_g11v0d16v0-table0.rst + + + +The symbol of the :model:`sky130_fd_pr__nfet_g5v0d16v0` (11V/16V NMOS FET) is shown below: + +|symbol-nfet_g11v0d16v0| + +The cross-section of the 11V/16VV NMOS FET is shown below. + +|cross-section-nfet_g11v0d16v0| + +.. |symbol-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/symbol-nfet_g11v0d16v0.svg +.. |cross-section-nfet_g11v0d16v0| image:: device-details/nfet_g11v0d16v0/cross-section-nfet_g11v0d16v0.svg + + 20V NMOS FET ------------ @@ -692,6 +659,156 @@ The cross-section of the 20V NMOS zero-VT FET is shown below. .. |cross-section-nfet_20v0_zvt| image:: device-details/nfet_20v0_zvt/cross-section-nfet_20v0_zvt.svg +20V PMOS FET +------------ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` +- Model Name: :model:`sky130_fd_pr__pfet_20v0` + +Operating Voltages where SPICE models are valid, subject to SOA limitations: + +- :math:`V_{DS} = 0` to -22V +- :math:`V_{GS} = 0` to -5.5V +- :math:`V_{BS} = 0` to +2.0V + +Details +~~~~~~~ + +The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences: + +- Longer drift region +- Longer poly gate +- Larger W/L +- Devices placed in pairs (drain in middle, sources on outside) + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/pfet_20v0/pfet_20v0-table0.rst + + + +The symbol of the :model:`sky130_fd_pr__pfet_20v0` (20V PMOS FET) is shown below. + +|symbol-pfet_20v0| + +The cross-section of the 20V PMOS FET is shown below. + +|cross-section-pfet_20v0| + +.. |symbol-pfet_20v0| image:: device-details/pfet_20v0/symbol-pfet_20v0.svg +.. |cross-section-pfet_20v0| image:: device-details/pfet_20v0/cross-section-pfet_20v0.svg + + +NMOS ESD FET +------------ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Model Name: :model:`sky130_fd_pr__esd_nfet_01v8`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to 11.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) +- :math:`V_{GS} = 0` to 5.0V (:model:`sky130_fd_pr__nfet_g5v0d10v5*`), 0 to 1.95V (:model:`sky130_fd_pr__nfet_01v8*`) +- :math:`V_{BS} = 0` to -5.5V, (:model:`sky130_fd_pr__nfet_g5v0d10v5`), +0.3 to -5.5V (:model:`sky130_fd_pr__nfet_05v0_nvt`), 0 to -1.95V (:model:`sky130_fd_pr__nfet_01v8*`) + +Details +~~~~~~~ + +The ESD FET’s differ from the regular NMOS devices in several aspects, most notably: + +- Increased isolation spacing from contacts to surrounding STI +- Increased drain contact-to-gate spacing +- Placement of n-well under the drain contacts + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/esd_nfet/esd_nfet-table0.rst + + + +The symbols of the :model:`sky130_fd_pr__esd_nfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_nfet_g5v0d10v5_nvt` (ESD NMOS FET) are shown below: + +|symbol-esd_nfet_g5v0d10v5| |symbol-esd_nfet_g5v0d10v5_nvt| + +The cross-section of the ESD NMOS FET is shown below. + +|cross-section-esd_nfet| + +.. |symbol-esd_nfet_g5v0d10v5| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5.svg +.. |symbol-esd_nfet_g5v0d10v5_nvt| image:: device-details/esd_nfet/symbol-esd_nfet_g5v0d10v5_nvt.svg +.. |cross-section-esd_nfet| image:: device-details/esd_nfet/cross-section-esd_nfet.svg + + +Diodes +------ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`diode` +- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pw2nd_05v5_nvt`, :model:`sky130_fd_pr__diode_pw2nd_05v5_lvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5_hvt`, :model:`sky130_fd_pr__diode_pd2nw_05v5_lvt`, :model:`sky130_fd_pr__model__parasitic__rf_diode_ps2nw`, :model:`sky130_fd_pr__model__parasitic__rf_diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_pw2dn`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`sky130_fd_pr__model__parasitic__diode_ps2nw`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)` +- Cell Name: :cell:`lvsdiode` +- Model Names: :model:`sky130_fd_pr__diode_pw2nd_05v5`, :model:`sky130_fd_pr__diode_pw2nd_11v0`, :model:`sky130_fd_pr__diode_pd2nw_05v5`, :model:`sky130_fd_pr__diode_pd2nw_11v0`, :model:`sky130_fd_pr__model__parasitic__diode_ps2dn`, :model:`dnwdiode_psub_victim`, :model:`dnwdiode_psub_aggressor`, :model:`nwdiode_victim`, :model:`nwdiode_aggressor`, :model:`xesd_ndiode_h_X`, :model:`xesd_ndiode_h_dnwl_X`, :model:`xesd_pdiode_h_X (X = 100 or 200 or 300)` + +Operating regime where SPICE models are valid + +- :math:`|V_{d0} – V_{d1}| = 0` to 5.0V + +Details +~~~~~~~ + + +.. include:: device-details/diodes/diodes-table0.rst + + + +Symbols for the diodes are shown below + +|symbol-diode-01| +|symbol-diode-02| +|symbol-diode-03| +|symbol-diode-04| +|symbol-diode-05| +|symbol-diode-06| +|symbol-diode-07| +|symbol-diode-08| +|symbol-diode-09| +|symbol-diode-10| +|symbol-diode-11| +|symbol-diode-12| +|symbol-diode-13| +|symbol-diode-14| +|symbol-diode-15| +|symbol-diode-16| +|symbol-diode-17| + +.. |symbol-diode-01| image:: device-details/diodes/symbol-diode-01.svg +.. |symbol-diode-02| image:: device-details/diodes/symbol-diode-02.svg +.. |symbol-diode-03| image:: device-details/diodes/symbol-diode-03.svg +.. |symbol-diode-04| image:: device-details/diodes/symbol-diode-04.svg +.. |symbol-diode-05| image:: device-details/diodes/symbol-diode-05.svg +.. |symbol-diode-06| image:: device-details/diodes/symbol-diode-06.svg +.. |symbol-diode-07| image:: device-details/diodes/symbol-diode-07.svg +.. |symbol-diode-08| image:: device-details/diodes/symbol-diode-08.svg +.. |symbol-diode-09| image:: device-details/diodes/symbol-diode-09.svg +.. |symbol-diode-10| image:: device-details/diodes/symbol-diode-10.svg +.. |symbol-diode-11| image:: device-details/diodes/symbol-diode-11.svg +.. |symbol-diode-12| image:: device-details/diodes/symbol-diode-12.svg +.. |symbol-diode-13| image:: device-details/diodes/symbol-diode-13.svg +.. |symbol-diode-14| image:: device-details/diodes/symbol-diode-14.svg +.. |symbol-diode-15| image:: device-details/diodes/symbol-diode-15.svg +.. |symbol-diode-16| image:: device-details/diodes/symbol-diode-16.svg +.. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg + + Bipolar (NPN) ------------- @@ -744,265 +861,6 @@ The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The pol .. |cross-section-npn_11v0| image:: device-details/npn_05v0/cross-section-npn_11v0.svg -5.0V/10.5V PMOS FET -------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` -- Model Name: :model:`sky130_fd_pr__pfet_g5v0d10v5`, :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` - -Operating Voltages where SPICE models are valid - -- :math:`V_{DS} = 0` to -11.0V -- :math:`V_{GS} = 0` to -5.5V -- :math:`V_{BS} = 0` to +5.5V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table0.rst - - - -Inverter gate delays are shown below: - - -.. include:: device-details/pfet_g5v0d10v5/pfet_g5v0d10v5-table1.rst - - - -The symbols of the :model:`sky130_fd_pr__pfet_g5v0d10v5` and :model:`sky130_fd_pr__esd_pfet_g5v0d10v5` (5.0V/10.5V PMOS FET) are shown below: - -|symbol-pfet_g5v0d10v5| |symbol-esd_pfet_g5v0d10v5| - -The cross-section of the 5.0V PMOS FET is shown below. - -|cross-section-pfet_g5v0d10v5| - -.. |symbol-pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/symbol-pfet_g5v0d10v5.svg -.. |symbol-esd_pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/symbol-esd_pfet_g5v0d10v5.svg -.. |cross-section-pfet_g5v0d10v5| image:: device-details/pfet_g5v0d10v5/cross-section-pfet_g5v0d10v5.svg - - -10V/16V PMOS FET ----------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` -- Model Name: :model:`sky130_fd_pr__pfet_g5v0d16v0` - -Operating Voltages where SPICE models are valid, subject to SOA limitations: - -- :math:`V_{DS} = 0` to -16V (\ :math:`V_{GS} = 0`\ ) -- :math:`V_{DS} = 0` to -10V (\ :math:`V_{GS} < 0`\ ) -- :math:`V_{GS} = 0` to -5.5V -- :math:`V_{BS} = 0` to +2.0V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/pfet_g5v0d16v0/pfet_g5v0d16v0-table0.rst - - - -The symbol of the :model:`sky130_fd_pr__pfet_g5v0d16v0` (10V/16V PMOS FET) is shown below: - -|symbol-pfet_g5v0d16v0| - -The cross-section of the 10V/16V PMOS FET is shown below. - -|cross-section-pfet_g5v0d16v0| - -.. |symbol-pfet_g5v0d16v0| image:: device-details/pfet_g5v0d16v0/symbol-pfet_g5v0d16v0.svg -.. |cross-section-pfet_g5v0d16v0| image:: device-details/pfet_g5v0d16v0/cross-section-pfet_g5v0d16v0.svg - - -1.8V high-VT PMOS FET ---------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` -- Model Name: :model:`sky130_fd_pr__pfet_01v8_hvt` - -Operating Voltages where SPICE models are valid - -- :math:`V_{DS} = 0` to -1.95V -- :math:`V_{GS} = 0` to -1.95V -- :math:`V_{BS} = -0.1` to +1.95V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table0.rst - - - -Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8_hvt` device combinations: - - -.. include:: device-details/pfet_01v8_hvt/pfet_01v8_hvt-table1.rst - - - -The symbol of the :model:`sky130_fd_pr__pfet_01v8_hvt` (1.8V high-VT PMOS FET) is shown below: - -|symbol-pfet_01v8_hvt| - -The cross-section of the high-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the higher :math:`V_T`) - -|cross-section-pfet_01v8_hvt| - -.. |symbol-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/symbol-pfet_01v8_hvt.svg -.. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg - - -1.8V low-VT PMOS FET --------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` -- Model Name: :model:`sky130_fd_pr__pfet_01v8_lvt` - -Operating Voltages where SPICE models are valid - -- :math:`V_{DS} = 0` to -1.95V -- :math:`V_{GS} = 0` to -1.95V -- :math:`V_{BS} = -0.1` to +1.95V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table0.rst - - - -Inverter Gate Delays using sky130_fd_pr__nfet_01v8_lvt/:model:`sky130_fd_pr__pfet_01v8_lvt` device combinations: - - -.. include:: device-details/pfet_01v8_lvt/pfet_01v8_lvt-table1.rst - - - -The symbol of the :model:`sky130_fd_pr__pfet_01v8_lvt` (1.8V low-VT PMOS FET) is shown below: - -|symbol-pfet_01v8_lvt| - -The cross-section of the low-VT PMOS FET is shown below. The cross-section is identical to the std PMOS FET except for the :math:`V_T` adjust implants (to achieve the lower :math:`V_T`) - -|cross-section-pfet_01v8_lvt| - -.. |symbol-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/symbol-pfet_01v8_lvt.svg -.. |cross-section-pfet_01v8_lvt| image:: device-details/pfet_01v8_lvt/cross-section-pfet_01v8_lvt.svg - - -1.8V PMOS FET -------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` -- Model Name: :model:`sky130_fd_pr__pfet_01v8` - -Operating Voltages where SPICE models are valid - -- :math:`V_{DS} = 0` to -1.95V -- :math:`V_{GS} = 0` to -1.95V -- :math:`V_{BS} = -0.1` to +1.95V - -Details -~~~~~~~ - -Major model output parameters are shown below and compared against the EDR (e-test) specs. - - -.. include:: device-details/pfet_01v8/pfet_01v8-table0.rst - - - -Inverter Gate Delays using sky130_fd_pr__nfet_01v8/:model:`sky130_fd_pr__pfet_01v8` device combinations: - - -.. include:: device-details/pfet_01v8/pfet_01v8-table1.rst - - - -The symbol of the :model:`sky130_fd_pr__pfet_01v8` (1.8V PMOS FET) is shown below: - -|symbol-pfet_01v8| - -The cross-section of the PMOS FET is shown below: - -|cross-section-pfet_01v8| - -.. |symbol-pfet_01v8| image:: device-details/pfet_01v8/symbol-pfet_01v8.svg -.. |cross-section-pfet_01v8| image:: device-details/pfet_01v8/cross-section-pfet_01v8.svg - - -20V PMOS FET ------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_extenddrain` -- Model Name: :model:`sky130_fd_pr__pfet_20v0` - -Operating Voltages where SPICE models are valid, subject to SOA limitations: - -- :math:`V_{DS} = 0` to -22V -- :math:`V_{GS} = 0` to -5.5V -- :math:`V_{BS} = 0` to +2.0V - -Details -~~~~~~~ - -The 20V NMOS FET has similar construction to the 11V/16V NMOS FET, with several differences: - -- Longer drift region -- Longer poly gate -- Larger W/L -- Devices placed in pairs (drain in middle, sources on outside) - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/pfet_20v0/pfet_20v0-table0.rst - - - -The symbol of the :model:`sky130_fd_pr__pfet_20v0` (20V PMOS FET) is shown below. - -|symbol-pfet_20v0| - -The cross-section of the 20V PMOS FET is shown below. - -|cross-section-pfet_20v0| - -.. |symbol-pfet_20v0| image:: device-details/pfet_20v0/symbol-pfet_20v0.svg -.. |cross-section-pfet_20v0| image:: device-details/pfet_20v0/cross-section-pfet_20v0.svg - - Bipolar (PNP) ------------- @@ -1050,6 +908,120 @@ No deep n-well exists in this device; the collector is the substrate. .. |cross-section-pnp_05v0| image:: device-details/pnp_05v0/cross-section-pnp_05v0.svg +SRAM cells +---------- + +The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays. + +|figure-10-schematics-of-the-single-port-sram| + +**Figure 10. Schematics of the Single Port SRAM.** + +A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019. + +Operating Voltages where SPICE models are valid + +- :math:`V_{DS} = 0` to 1.8V +- :math:`V_{GS} = 0` to 1.8V +- :math:`V_{BS} = 0` to -1.8V + +Details +~~~~~~~ + +N-pass FET (SRAM) +^^^^^^^^^^^^^^^^^ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_pass` + + +.. include:: device-details/special_sram/special_sram-table0.rst + + + +N-latch FET (SRAM) +^^^^^^^^^^^^^^^^^^ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` +- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_latch` + + +.. include:: device-details/special_sram/special_sram-table1.rst + + + +P-latch FET (SRAM) +^^^^^^^^^^^^^^^^^^ + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` +- Model Name (SRAM): :model:`sky130_fd_pr__special_pfet_pass` + + +.. include:: device-details/special_sram/special_sram-table2.rst + + + +.. |figure-10-schematics-of-the-single-port-sram| image:: device-details/special_sram/figure-10-schematics-of-the-single-port-sram.svg + + +SONOS cells +----------- + +The SKY130 process currently supports two SONOS flash memory cells: + +- The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C +- The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C. + +Spice models for the memory cells exist for multiple conditions: + + +.. include:: device-details/special_sonosfet/special_sonosfet-table0.rst + + + +Program and Erase characteristics are described in more detail in the ***S8 Nonvolatile Technology Spec*** (001-08712), and summarized below: + + +.. include:: device-details/special_sonosfet/special_sonosfet-table1.rst + + + +Endurance behavior is illustrated below (100K cycles guaranteed): + +|sonos-erase-program| + +Data retention behavior is shown below at 85C\ |sonos-data-retention| + +E-test parameters are summarized below for both original and star cells: + + +.. include:: device-details/special_sonosfet/special_sonosfet-table2.rst + + + +The schematic for the 2-T SONOS memory cell is shown below: + +|schematic-sonos-cell| + +The cross-section of the 2-T SONOS cell is shown below. + +|cross-section-sonos-cell| + +.. |sonos-erase-program| image:: device-details/special_sonosfet/sonos-erase-program.svg +.. |sonos-data-retention| image:: device-details/special_sonosfet/sonos-data-retention.svg +.. |schematic-sonos-cell| image:: device-details/special_sonosfet/schematic-sonos-cell.svg +.. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg + + Generic Resistors ----------------- @@ -1242,117 +1214,145 @@ A generic version of the poly resistor is also available, which permits user inp .. |symbol-res_xhigh_po| image:: device-details/res_xhigh/symbol-res_xhigh_po.svg -SONOS cells ------------ +MiM Capacitor +------------- -The SKY130 process currently supports two SONOS flash memory cells: +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ -- The original cell is supported in the S8PFHD, S8PHRC and S8PFN-20 technology options, with operating temperatures from -55°C to +155°C -- The “star” cell is supported in the S8PHIRS technology option. Its cell size is approximately 25% smaller than the original cell, but its temperature range is restricted to -40°C to +125°C. - -Spice models for the memory cells exist for multiple conditions: - - -.. include:: device-details/special_sonosfet/special_sonosfet-table0.rst - - - -Program and Erase characteristics are described in more detail in the ***S8 Nonvolatile Technology Spec*** (001-08712), and summarized below: - - -.. include:: device-details/special_sonosfet/special_sonosfet-table1.rst - - - -Endurance behavior is illustrated below (100K cycles guaranteed): - -|sonos-erase-program| - -Data retention behavior is shown below at 85C\ |sonos-data-retention| - -E-test parameters are summarized below for both original and star cells: - - -.. include:: device-details/special_sonosfet/special_sonosfet-table2.rst - - - -The schematic for the 2-T SONOS memory cell is shown below: - -|schematic-sonos-cell| - -The cross-section of the 2-T SONOS cell is shown below. - -|cross-section-sonos-cell| - -.. |sonos-erase-program| image:: device-details/special_sonosfet/sonos-erase-program.svg -.. |sonos-data-retention| image:: device-details/special_sonosfet/sonos-data-retention.svg -.. |schematic-sonos-cell| image:: device-details/special_sonosfet/schematic-sonos-cell.svg -.. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg - - -SRAM cells ----------- - -The SKY130 process currently supports only single-port SRAM’s, which are contained in hard-IP libraries. These cells are constructed with smaller design rules (Table 9), along with OPC (optical proximity correction) techniques, to achieve small memory cells. Use of the memory cells or their devices outside the specific IP is prohibited. The schematic for the SRAM is shown below in Figure 10. This cell is available in the S8 IP offerings and is monitored at e-test through the use of “pinned out” devices within the specific arrays. - -|figure-10-schematics-of-the-single-port-sram| - -**Figure 10. Schematics of the Single Port SRAM.** - -A Dual-Port SRAM is currently being designed using a similar approach. Compilers for the SP and DP SRAM’s will be available end-2019. +- Cell Name: :cell:`sky130_fd_pr__cap_mim_m3__base`, :cell:`sky130_fd_pr__cap_mim_m4__base` +- Model Names: :model:`sky130_fd_pr__model__cap_mim`, :model:`sky130_fd_pr__cap_mim_m4` Operating Voltages where SPICE models are valid -- :math:`V_{DS} = 0` to 1.8V -- :math:`V_{GS} = 0` to 1.8V -- :math:`V_{BS} = 0` to -1.8V +- :math:`|V_{c0} – V_{c1}| = 0` to 5.0V Details ~~~~~~~ -N-pass FET (SRAM) -^^^^^^^^^^^^^^^^^ +The MiM capacitor is constructed using a thin dielectric over metal, followed by a thin conductor layer on top of the dielectric. There are two possible constructions: + +- CAPM over Metal-3 +- CAP2M over Metal-4 + +The constructions are identical, and the capacitors may be stacked to maximize total capacitance. + +Electrical specs are listed below: + + +.. include:: device-details/cap_mim/cap_mim-table0.rst + + + +The symbol for the MiM capacitor is shown below. Note that the cap model is a sub-circuit which accounts for the parasitic contact resistance and the parasitic capacitance from the bottom plate to substrate. + +|symbol-cap_mim| + +Cell name + +M \* W \* L + +Calc capacitance + +The cross-section of the “stacked” MiM capacitor is shown below: + +|cross-section-cap_mim| + +.. |symbol-cap_mim| image:: device-details/cap_mim/symbol-cap_mim.svg +.. |cross-section-cap_mim| image:: device-details/cap_mim/cross-section-cap_mim.svg + + +Vertical Parallel Plate (VPP) capacitors +---------------------------------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` -- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_pass` +- Cell Name: :cell:`sky130_fd_pr__cap_vpp_XXpXxYYpY_{MM}(_shield(SS)*)(_float(FF)*)(_(VVVV))` +- Model Names: :model:`sky130_fd_pr__cap_vpp_*` + + - X and Y are size dimentions + - MM refers to the layers which are used for the capacitance + - SS refers to the layers which are used as shields (`noshield` when no shield is used) + - FF refers to the layers which are floating. + - VVVVV refers to the "variant" when there are multiple devices of the same configuration + +Operating Voltages where SPICE models are valid + +- :math:`|V_{c0} – V_{c1}| = 0` to 5.5V + +Details +~~~~~~~ + +The VPP caps utilize the tight spacings of the metal lines to create capacitors using the available metal layers. The fingers go in opposite directions to minimize alignment-related variability, and the capacitor sits on field oxide to minimize silicon capacitance effects. A schematic diagram of the layout is shown below: + +.. todo:: + + M3 + + **M2** + + LI + + M1 + + LAYOUT of M2, M3, M4 + + LAYOUT of LI and M1 (with POLY sheet) + + **POLY** + + **M4** + +These capacitors are fixed-size, and they can be connected together to multiply the effective capacitance of a given node. There are two different constructions. + +Parallel VPP Capacitors +^^^^^^^^^^^^^^^^^^^^^^^ + +These are older versions, where stacked metal lines run parallel: -.. include:: device-details/special_sram/special_sram-table0.rst +- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2_noshield` (M1 \|\| M2 only, 7.84 x 8.58) +- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield_o2` (M1 \|\| M2 only, 4.38 x 4.59) +- :model:`sky130_fd_pr__cap_vpp_02p4x04p6_m1m2_noshield` (M1 \|\| M2 only, 2.19 x 4.59) +- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2_noshield` (M1 :sub:`┴` M2, 4.4 x 4.6, 4 quadrants) +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2_noshield` (M1 :sub:`┴` M2, 11.5 x 11.7, 4 quadrants) +- :model:`sky130_fd_pr__cap_vpp_44p7x23p1_pol1m1m2m3m4m5_noshield` +- :model:`sky130_fd_pr__cap_vpp_02p7x06p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 5.0) +- :model:`sky130_fd_pr__cap_vpp_02p9x06p1_m1m2m3m4_shieldl1_fingercap2` (M1 \|\| M2 \|\| M3 \|\| M4, 2.85 x 5.0) +- :model:`sky130_fd_pr__cap_vpp_02p7x11p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 10.0) +- :model:`sky130_fd_pr__cap_vpp_02p7x21p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 20.0) +- :model:`sky130_fd_pr__cap_vpp_02p7x41p1_m1m2m3m4_shieldl1_fingercap` (M1 \|\| M2 \|\| M3 \|\| M4, 2.7 x 40.0) + +The symbol for these capacitors is shown below. The terminals c0 and c1 represent the two sides of the capacitor, with b as the body (sub or well). + +|symbol-cap_vpp-parallel| + +Perpendicular VPP Capacitors +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +These are newer versions, where stacked metal lines run perpendicular and there are shields on top and bottom: + +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldm5` (11.5x11.7, with M5 shield) +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3m4_shieldpom5` (11.5x11.7, with poly and M5 shield) +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3m4_shieldl1m5` (11.5x11.7, with LI and M5 shield) +- :model:`sky130_fd_pr__cap_vpp_04p4x04p6_m1m2m3_shieldl1m5_floatm4` (4.4x4.6, M3 float, LI / M5 shield) +- :model:`sky130_fd_pr__cap_vpp_08p6x07p8_m1m2m3_shieldl1m5_floatm4` (8.6x7.9, M3 float, LI / M5 shield) +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_m1m2m3_shieldl1m5_floatm4` (11.5x11.7, M3 float, LI / M5 shield) +- :model:`sky130_fd_pr__cap_vpp_11p5x11p7_l1m1m2m3_shieldm4` (11.5x11.7, with M4 shield) +- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_l1m1m2m3_shieldpom4` (6.8x6.1, with poly and M4 shield) +- :model:`sky130_fd_pr__cap_vpp_06p8x06p1_m1m2m3_shieldl1m4` (6.8x6.1, with LI and M4 shield) +- :model:`sky130_fd_pr__cap_vpp_11p3x11p8_l1m1m2m3m4_shieldm5` (11.5x11.7, over 2 :model:`sky130_fd_pr__nfet_05v0_nvt` of 10/4 each) + +The symbol for these capacitors is shown below. The terminals c0 and c1 are the two capacitor terminals, “top” represents the top shield and “sub” the bottom shield. + +|symbol-cap_vpp-perpendicular| + +The capacitors are fixed-size elements and must be used as-is; they can be used in multiples. +.. include:: device-details/cap_vpp/cap_vpp-table0.rst -N-latch FET (SRAM) -^^^^^^^^^^^^^^^^^^ - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__nfet_01v8` -- Model Name (SRAM): :model:`sky130_fd_pr__special_nfet_latch` - - -.. include:: device-details/special_sram/special_sram-table1.rst - - - -P-latch FET (SRAM) -^^^^^^^^^^^^^^^^^^ - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__pfet_01v8` -- Model Name (SRAM): :model:`sky130_fd_pr__special_pfet_pass` - - -.. include:: device-details/special_sram/special_sram-table2.rst - - - -.. |figure-10-schematics-of-the-single-port-sram| image:: device-details/special_sram/figure-10-schematics-of-the-single-port-sram.svg - +.. |symbol-cap_vpp-parallel| image:: device-details/cap_vpp/symbol-cap_vpp-parallel.svg +.. |symbol-cap_vpp-perpendicular| image:: device-details/cap_vpp/symbol-cap_vpp-perpendicular.svg diff --git a/docs/rules/device-details/cap_var/index.rst b/docs/rules/device-details/cap_var/index.rst index 3209cee..10691a9 100644 --- a/docs/rules/device-details/cap_var/index.rst +++ b/docs/rules/device-details/cap_var/index.rst @@ -1,5 +1,5 @@ -Varactors ---------- +1.8V Accumulation-Mode MOS Varactors +------------------------------------ Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ From 995acd5dfa0589d156619694db011873796a5d2d Mon Sep 17 00:00:00 2001 From: Stefan Biereigel Date: Mon, 31 Oct 2022 22:54:16 +0100 Subject: [PATCH 38/40] device section name consistency fixes --- docs/rules/device-details.py | 2 +- docs/rules/device-details.rst | 98 +++++++++---------- docs/rules/device-details/cap_mim/index.rst | 4 +- docs/rules/device-details/cap_var/index.rst | 2 +- docs/rules/device-details/esd_nfet/index.rst | 2 +- .../device-details/nfet_20v0_zvt/index.rst | 2 +- docs/rules/device-details/npn_05v0/index.rst | 4 +- docs/rules/device-details/pnp_05v0/index.rst | 4 +- .../device-details/res_generic/index.rst | 2 +- 9 files changed, 60 insertions(+), 60 deletions(-) diff --git a/docs/rules/device-details.py b/docs/rules/device-details.py index 2a84c79..bb809ee 100755 --- a/docs/rules/device-details.py +++ b/docs/rules/device-details.py @@ -29,9 +29,9 @@ device_list = [ # 20V MOS "nfet_20v0", - "nfet_20v0_iso", "nfet_20v0_nvt", "nfet_20v0_zvt", + "nfet_20v0_iso", "pfet_20v0", # ESD MOS diff --git a/docs/rules/device-details.rst b/docs/rules/device-details.rst index 2997b36..805a67a 100644 --- a/docs/rules/device-details.rst +++ b/docs/rules/device-details.rst @@ -216,7 +216,7 @@ The cross-section of the high-VT PMOS FET is shown below. The cross-section is i .. |cross-section-pfet_01v8_hvt| image:: device-details/pfet_01v8_hvt/cross-section-pfet_01v8_hvt.svg -1.8V Accumulation-Mode MOS Varactors +1.8V accumulation-mode MOS varactors ------------------------------------ Spice Model Information @@ -545,45 +545,6 @@ The cross-section of the 20V NMOS FET is shown below. .. |cross-section-nfet_20v0| image:: device-details/nfet_20v0/cross-section-nfet_20v0.svg -20V isolated NMOS FET ---------------------- - -Spice Model Information -~~~~~~~~~~~~~~~~~~~~~~~ - -- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` -- Model Name: :model:`sky130_fd_pr__nfet_20v0_iso` - -Operating Voltages where SPICE models are valid, subject to SOA limitations: - -- :math:`V_{DS} = 0` to +22V -- :math:`V_{GS} = 0` to 5.5V -- :math:`V_{BS} = 0` to -2.0V - -Details -~~~~~~~ - -The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground). - -Major model output parameters are shown below and compared against the EDR (e-test) specs - - -.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst - - - -The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below. - -|symbol-nfet_20v0_iso| - -The cross-section of the 20V isolated NMOS FET is shown below. - -|cross-section-nfet_20v0_iso| - -.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg -.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg - - 20V native NMOS FET ------------------- @@ -623,7 +584,7 @@ The cross-section of the 20V native NMOS FET is shown below. .. |cross-section-nfet_20v0_nvt| image:: device-details/nfet_20v0_nvt/cross-section-nfet_20v0_nvt.svg -20V NMOS zero-VT FET +20V zero-VT NMOS FET -------------------- Spice Model Information @@ -659,6 +620,45 @@ The cross-section of the 20V NMOS zero-VT FET is shown below. .. |cross-section-nfet_20v0_zvt| image:: device-details/nfet_20v0_zvt/cross-section-nfet_20v0_zvt.svg +20V isolated NMOS FET +--------------------- + +Spice Model Information +~~~~~~~~~~~~~~~~~~~~~~~ + +- Cell Name: :cell:`sky130_fd_pr__nfet_extenddrain` +- Model Name: :model:`sky130_fd_pr__nfet_20v0_iso` + +Operating Voltages where SPICE models are valid, subject to SOA limitations: + +- :math:`V_{DS} = 0` to +22V +- :math:`V_{GS} = 0` to 5.5V +- :math:`V_{BS} = 0` to -2.0V + +Details +~~~~~~~ + +The 20V isolated NMOS FET has the same construction as the 20V NMOS FET, but is built over a Deep N-well. This permits the p-well to be isolated from the substrate and permit “high-side” usage (where the PW body is held above ground). + +Major model output parameters are shown below and compared against the EDR (e-test) specs + + +.. include:: device-details/nfet_20v0_iso/nfet_20v0_iso-table0.rst + + + +The symbol of the :model:`sky130_fd_pr__nfet_20v0_iso` (20V isolated NMOS FET) is shown below. + +|symbol-nfet_20v0_iso| + +The cross-section of the 20V isolated NMOS FET is shown below. + +|cross-section-nfet_20v0_iso| + +.. |symbol-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/symbol-nfet_20v0_iso.svg +.. |cross-section-nfet_20v0_iso| image:: device-details/nfet_20v0_iso/cross-section-nfet_20v0_iso.svg + + 20V PMOS FET ------------ @@ -703,7 +703,7 @@ The cross-section of the 20V PMOS FET is shown below. .. |cross-section-pfet_20v0| image:: device-details/pfet_20v0/cross-section-pfet_20v0.svg -NMOS ESD FET +ESD NMOS FET ------------ Spice Model Information @@ -809,8 +809,8 @@ Symbols for the diodes are shown below .. |symbol-diode-17| image:: device-details/diodes/symbol-diode-17.svg -Bipolar (NPN) -------------- +Bipolar NPN transistor +---------------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ @@ -861,8 +861,8 @@ The cross-section of the :model:`sky130_fd_pr__npn_11v0` is shown below. The pol .. |cross-section-npn_11v0| image:: device-details/npn_05v0/cross-section-npn_11v0.svg -Bipolar (PNP) -------------- +Bipolar PNP transistor +---------------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ @@ -1022,7 +1022,7 @@ The cross-section of the 2-T SONOS cell is shown below. .. |cross-section-sonos-cell| image:: device-details/special_sonosfet/cross-section-sonos-cell.svg -Generic Resistors +Generic resistors ----------------- Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements. @@ -1214,8 +1214,8 @@ A generic version of the poly resistor is also available, which permits user inp .. |symbol-res_xhigh_po| image:: device-details/res_xhigh/symbol-res_xhigh_po.svg -MiM Capacitor -------------- +MiM capacitors +-------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/rules/device-details/cap_mim/index.rst b/docs/rules/device-details/cap_mim/index.rst index 6a3958f..16ed45f 100644 --- a/docs/rules/device-details/cap_mim/index.rst +++ b/docs/rules/device-details/cap_mim/index.rst @@ -1,5 +1,5 @@ -MiM Capacitor -------------- +MiM capacitors +-------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/rules/device-details/cap_var/index.rst b/docs/rules/device-details/cap_var/index.rst index 10691a9..9383211 100644 --- a/docs/rules/device-details/cap_var/index.rst +++ b/docs/rules/device-details/cap_var/index.rst @@ -1,4 +1,4 @@ -1.8V Accumulation-Mode MOS Varactors +1.8V accumulation-mode MOS varactors ------------------------------------ Spice Model Information diff --git a/docs/rules/device-details/esd_nfet/index.rst b/docs/rules/device-details/esd_nfet/index.rst index 1d57c06..8f3e89c 100644 --- a/docs/rules/device-details/esd_nfet/index.rst +++ b/docs/rules/device-details/esd_nfet/index.rst @@ -1,4 +1,4 @@ -NMOS ESD FET +ESD NMOS FET ------------ Spice Model Information diff --git a/docs/rules/device-details/nfet_20v0_zvt/index.rst b/docs/rules/device-details/nfet_20v0_zvt/index.rst index f02630c..a1e7648 100644 --- a/docs/rules/device-details/nfet_20v0_zvt/index.rst +++ b/docs/rules/device-details/nfet_20v0_zvt/index.rst @@ -1,4 +1,4 @@ -20V NMOS zero-VT FET +20V zero-VT NMOS FET -------------------- Spice Model Information diff --git a/docs/rules/device-details/npn_05v0/index.rst b/docs/rules/device-details/npn_05v0/index.rst index 7ec820d..771e840 100644 --- a/docs/rules/device-details/npn_05v0/index.rst +++ b/docs/rules/device-details/npn_05v0/index.rst @@ -1,5 +1,5 @@ -Bipolar (NPN) -------------- +Bipolar NPN transistor +---------------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/rules/device-details/pnp_05v0/index.rst b/docs/rules/device-details/pnp_05v0/index.rst index 0ffc275..38ba1dc 100644 --- a/docs/rules/device-details/pnp_05v0/index.rst +++ b/docs/rules/device-details/pnp_05v0/index.rst @@ -1,5 +1,5 @@ -Bipolar (PNP) -------------- +Bipolar PNP transistor +---------------------- Spice Model Information ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/rules/device-details/res_generic/index.rst b/docs/rules/device-details/res_generic/index.rst index f565c73..98d616d 100644 --- a/docs/rules/device-details/res_generic/index.rst +++ b/docs/rules/device-details/res_generic/index.rst @@ -1,4 +1,4 @@ -Generic Resistors +Generic resistors ----------------- Generic resistors are supported in the PDK but are not recommended for analog applications. Resistor values will be extracted from the layout as long as the resistor layer is utilized, for LVS against schematic elements. From 9c783ae8e84a792b54faa4b928fa9e9dc56faca4 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Thu, 10 Nov 2022 09:58:38 -0800 Subject: [PATCH 39/40] Adding a blocker label. Fixes #405. --- .github/labels.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/labels.yml b/.github/labels.yml index 6f32df8..968c362 100644 --- a/.github/labels.yml +++ b/.github/labels.yml @@ -51,6 +51,10 @@ description: "Item which references a specific open task which needs finishing." color: "57dbba" # FIXME: blueish +- name: "type-blocker" + description: "Issue which is blocking a launch." + color: "ff0000" # Very Red + ########################################################################## # Labels related to files found in the repository # From 6238c1e98e590d1a19d0d8ec2609bdcd5481dbd8 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Fri, 6 Jan 2023 17:45:07 -0800 Subject: [PATCH 40/40] Update `make-env` submodule. Fixes the issue caused by https://github.com/conda/conda/issues/10431 by including https://github.com/SymbiFlow/make-env/pull/31 Signed-off-by: Tim 'mithro' Ansell --- third_party/make-env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/third_party/make-env b/third_party/make-env index 9b07ad2..33b80bd 160000 --- a/third_party/make-env +++ b/third_party/make-env @@ -1 +1 @@ -Subproject commit 9b07ad2bb62fbf8af789c9e4669715c974b4912d +Subproject commit 33b80bd32c30fb8affd0fd5cda544d1bca075593