There are seven standard cell libraries provided directly by the SkyWater Technology foundry available for use on SKY130 designs, which differ in intended applications and come in three separate cell heights.
Libraries :lib:`sky130_fd_sc_hs` (high speed), :lib:`sky130_fd_sc_ms` (medium speed), :lib:`sky130_fd_sc_ls` (low speed), and :lib:`sky130_fd_sc_lp` (low power) are compatible in size, with a 0.48 x 3.33um site, equivalent to about 11 :layer:`met1` tracks.
Libraries :lib:`sky130_fd_sc_hd` (high density) and :lib:`sky130_fd_sc_hdll` (high density, low leakage) contain standard cells that are smaller, utilizing a 0.46 x 2.72um site, equivalent to 9 :layer:`met1` tracks.
The libraries uses 4 terminal transistors throughout. Individual cells do not have tap in them for the most part (there are a few exceptions). Instead, there are tap cells provided that allow for a staggered tap grid to be placed and connected to allow for body biasing, sleep mode support, and latchup protection.
Compared to :lib:`sky130_fd_sc_ls`, this library enables higher routed gated density, lower dynamic power consumption, and comparable timing and leakage power. As a trade-off it has lower drive strength and does not support any drop in replacement medium or high speed library.
The :lib:`sky130_fd_sc_hdll` library is a low leakage high density standard cell library.
Compared to :lib:`sky130_fd_sc_hd`, this library enables 5-10X lower leakage power, but the same X, Y pin grids, routing layer pitches, and cell height.
Blocks should be DRC clean when intermingled with :lib:`sky130_fd_sc_hd` cells.
Raw gate density (number of :cell:`sky130_fd_sc_hdll__nand2_1` gates able to fit in 1mm2) for :lib:`sky130_fd_sc_hd` is 266kGates/mm2 and 200kGates/mm2 for :lib:`sky130_fd_sc_hdll`.
- Includes integrating clock-gating cells to reduce active power during non-sleep modes
- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
- Multi-voltage domain library cells are provided
- Routed Gate Density is 120 kGates/mm^2
- leakage @ttleak\_1.80v\_25C (no body bias) is 0.08 nA / kGate
-:cell:`sky130_fd_sc_XX__buf_16` max cap (ss\_1.60v\_-40C, in/out tran=1.5ns) < 1 pF
- Multi-Voltage Design Support
- Body Bias-able
:lib:`sky130_fd_sc_hs` - Low Voltage (<2.0V), High Speed, Standard Cell Library
:lib:`sky130_fd_sc_hs` cells are drop-in compatible with :lib:`sky130_fd_sc_ms`a or :lib:`sky130_fd_sc_ls` for the same function and drive strength. :lib:`sky130_fd_sc_hs` has the highest speed and the highest leakage of these.
All logic cells are implemented with low voltage transistors and should be powered within the limits of those transistors. Specifically, the timing and power models are valid from 1.60V up to 1.95V, with timing data included for 10% and 20% dynamic IR drop analysis.
All cells are functional at 1.2v. The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
:lib:`sky130_fd_sc_ms` - Low Voltage (<2.0V), Medium Speed, Standard Cell Library
:lib:`sky130_fd_sc_ms` is drop-in compatible with :lib:`sky130_fd_sc_ls` or :lib:`sky130_fd_sc_hs` libraries for cells of the same function and drive strength. :lib:`sky130_fd_sc_ms` cells have medium speed and leakage.
:lib:`sky130_fd_sc_ms` is implemented with low voltage transistors; timing and power models are valid from 1.60V up to 1.95V. All cells are functional at 1.2v.
The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
- The library supports low leakage sleep mode via state retention flops
- Includes integrating clock-gating cells to reduce active power during non-sleep modes
- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
- Library details:
- Inverters and buffers: 48
- AND, OR, NAND, NOR gates: 86
- Exclusive-OR and Exclusive-NOR: 12
- Inverted And-Or and Inverted Or-And: 71
- And-Or and Or-And: 68
- Adders, Comparators and Multiplexers: 33
- Latches and filp-flops: 68
- Low Power Flow Cells: 42
- UDB custom cells: 17
:lib:`sky130_fd_sc_ls` - Low Voltage (<2.0V), Low Speed, Standard Cell Library
:lib:`sky130_fd_sc_ls` cells are drop-in compatible with :lib:`sky130_fd_sc_ms`a or :lib:`sky130_fd_sc_hs` for the same function and drive strength. :lib:`sky130_fd_sc_ls` has the lowest speed and the lowest leakage of these.
:lib:`sky130_fd_sc_ls` is implemented with low voltage transistors; timing and power models are valid from 1.60V up to 1.95V. All cells are functional at 1.2v.
The low to high level shifter cells are capable of shifting from 1.2v to 1.95v.
- The library supports low leakage sleep mode via sleep transistors
- Includes integrating clock-gating cells to reduce active power during non-sleep modes
- Latches and flip-flops in the library have a scan equivalent implementation to enable scan chain creation and testing supported by the synthesis tools
- Drop-in compatible with :lib:`sky130_fd_sc_ms` and :lib:`sky130_fd_sc_hs` libraries
- Only the high to low level-shifters are functional at 1v (:cell:`sky130_fd_sc_ls__lpflow_lsbuf_hl_*`). The low to high level-shifters (:cell:`sky130_fd_sc_ls__lpflow_lsbuf_lh_*`) are not functional at 1v as the threshold voltages of the FETs are not enough to flip the state.
- Library details:
- Inverters and buffers: 48
- AND, OR, NAND, NOR gates: 86
- Exclusive-OR and Exclusive-NOR: 12
- Inverted And-Or and Inverted Or-And: 71
- And-Or and Or-And: 68
- Adders, Comparators and Multiplexers: 37
- Latches and filp-flops: 68
- Low Power Flow Cells: 66
- Macro Cells: 5
- UDB Custom Cells: 21
:lib:`sky130_fd_sc_lp` - Low Voltage (<2.0V), Low Power, Standard Cell Library
:lib:`sky130_fd_sc_lp` is the largest of the SKY130 standard cell libraries at nearly 750 cells. All logic cells are implemented with low voltage transistors and should be powered within the limits of those transistors. Specifically, the timing and power models are valid from 1.55V up to 2.0V.
The :lib:`sky130_fd_sc_hvl` library has the smallest cell count of the SKY130 standard cell libraries, but is the only one that enables 5V tolerant logic blocks. All logic cells are implemented with 5v tolerant transistors; timing and power models are valid from 1.65v to 5.5v. The low voltage to high voltage level shifter is functional shifting from 1.2v to 5.5v.
Routed should be >= 100kGates/mm2. Due to the gate length for these high voltage transistors, the actual gate density is lower than 170kGates/mm2. The size of a 2-input NAND gate in this library is actually 5 grids wide, whereas the 170k calculation is based on a gate that is 3 grids wide. With a 5 grid wide gate, the raw gate density is 102kGates/mm2.
