coriolis/crlcore/etc/45/ispd18/plugins.conf

28 lines
1.2 KiB
Python

# -*- Mode:Python; explicit-buffer-name: "plugins.conf<ispd18>" -*-
import helpers
# Contains the layout (shared by all technologies).
#execfile( helpers.sysConfDir+'/common/plugins.conf' )
# WARNING: Those values have not been adjusted yet for this technologies.
# Must be done.
#
# Parameters for chip plugin.
parametersTable = \
( ("chip.block.rails.count" , TypeInt , 5 )
, ("chip.block.rails.hWidth" , TypeInt , 24 )
, ("chip.block.rails.vWidth" , TypeInt , 24 )
, ("chip.block.rails.hSpacing" , TypeInt , 12 )
, ("chip.block.rails.vSpacing" , TypeInt , 12 )
, ('chip.pad.pck' , TypeString, 'pck_mpx')
, ('chip.pad.pvddick' , TypeString, 'pvddick_mpx')
, ('chip.pad.pvssick' , TypeString, 'pvssick_mpx')
, ('chip.pad.pvddeck' , TypeString, 'pvddeck_mpx')
, ('chip.pad.pvsseck' , TypeString, 'pvsseck_mpx')
, ('clockTree.minimumSide' , TypeInt , 1000)
, ('clockTree.buffer' , TypeString, 'buf_x2')
, ('clockTree.placerEngine' , TypeString, 'Etesian')
)