coriolis/crlcore/etc/cmos/technology.conf

163 lines
6.8 KiB
Python

# -*- Mode:Python; explicit-buffer-name: "technology.conf<cmos>" -*-
import helpers
# The informations here are extracted from the Alliance ".rds" file,
# and must be coherent with it.
#
# Provides standard settings for:
# - <viewerConfig>
# - <realLayersTable>
# - <symbolicLayersTable>
# - <workingLayersTable>
execfile( helpers.sysConfDir+'/common/technology.conf' )
# Format of <symbolicRulesTable>:
# Each entry is a pair of (string, value).
# * string: a synthetic way to designate the symbolic layer on which
# it applies, an optional real layer in case where there is
# more than one, and the dimension name.
# * value : the rule (dimension) value expressed in lambda.
symbolicRulesTable = \
( ('NWELL.nWell.extention.cap' , 0.0)
, ('PWELL.pWell.extention.cap' , 0.0)
, ('NTIE.minimum.width' , 3.0)
, ('NTIE.nWell.extention.cap' , 1.5)
, ('NTIE.nWell.extention.width' , 0.5)
, ('NTIE.nImplant.extention.cap' , 1.0)
, ('NTIE.nImplant.extention.width' , 0.5)
, ('NTIE.active.extention.cap' , 0.5)
, ('NTIE.active.extention.width' , 0.0)
, ('PTIE.minimum.width' , 3.0)
, ('PTIE.pWell.extention.cap' , 1.5)
, ('PTIE.pWell.extention.width' , 0.5)
, ('PTIE.pImplant.extention.cap' , 1.0)
, ('PTIE.pImplant.extention.width' , 0.5)
, ('PTIE.active.extention.cap' , 0.5)
, ('PTIE.active.extention.width' , 0.0)
, ('NDIF.minimum.width' , 3.0)
, ('NDIF.nImplant.extention.cap' , 1.0)
, ('NDIF.nImplant.extention.width' , 0.5)
, ('NDIF.active.extention.cap' , 0.5)
, ('NDIF.active.extention.width' , 0.0)
, ('PDIF.minimum.width' , 3.0)
, ('PDIF.pImplant.extention.cap' , 1.0)
, ('PDIF.pImplant.extention.width' , 0.5)
, ('PDIF.active.extention.cap' , 0.5)
, ('PDIF.active.extention.width' , 0.0)
, ('GATE.minimum.width' , 1.0)
, ('GATE.poly.extention.cap' , 1.5)
, ('NTRANS.minimum.width' , 1.0)
, ('NTRANS.nImplant.extention.cap' , -1.0)
, ('NTRANS.nImplant.extention.width' , 2.5)
, ('NTRANS.active.extention.cap' , -1.5)
, ('NTRANS.active.extention.width' , 2.0)
, ('PTRANS.minimum.width' , 1.0)
, ('PTRANS.nWell.extention.cap' , -1.0)
, ('PTRANS.nWell.extention.width' , 4.5)
, ('PTRANS.pImplant.extention.cap' , -1.0)
, ('PTRANS.pImplant.extention.width' , 4.0)
, ('PTRANS.active.extention.cap' , -1.5)
, ('PTRANS.active.extention.width' , 3.0)
, ('POLY.minimum.width' , 1.0)
, ('POLY.poly.extention.cap' , 0.5)
, ('POLY2.minimum.width' , 1.0)
, ('POLY2.poly.extention.cap' , 0.5)
# Routing Layers.
, ('METAL1.minimum.width' , 1.0)
, ('METAL1.metal1.extention.cap' , 0.5)
, ('METAL2.minimum.width' , 1.0)
, ('METAL2.metal2.extention.cap' , 1.0)
, ('METAL3.minimum.width' , 1.0)
, ('METAL3.metal3.extention.cap' , 1.0)
, ('METAL4.minimum.width' , 1.0)
, ('METAL4.metal4.extention.cap' , 1.0)
, ('METAL5.minimum.width' , 2.0)
, ('METAL5.metal5.extention.cap' , 1.0)
, ('METAL6.minimum.width' , 2.0)
, ('METAL6.metal6.extention.cap' , 1.0)
, ('METAL7.minimum.width' , 2.0)
, ('METAL7.metal6.extention.cap' , 1.0)
, ('METAL8.minimum.width' , 2.0)
, ('METAL8.metal6.extention.cap' , 1.0)
# Contacts (i.e. Active <--> Metal).
, ('CONT_BODY_N.minimum.side' , 1.0)
, ('CONT_BODY_N.nWell.enclosure' , 1.5)
, ('CONT_BODY_N.nImplant.enclosure' , 1.5)
, ('CONT_BODY_N.active.enclosure' , 1.0)
, ('CONT_BODY_N.metal1.enclosure' , 0.5)
, ('CONT_BODY_P.minimum.side' , 1.0)
, ('CONT_BODY_P.pWell.enclosure' , 1.5)
, ('CONT_BODY_P.pImplant.enclosure' , 1.5)
, ('CONT_BODY_P.active.enclosure' , 1.0)
, ('CONT_BODY_P.metal1.enclosure' , 0.5)
, ('CONT_DIF_N.minimum.side' , 1.0)
, ('CONT_DIF_N.nImplant.enclosure' , 1.0)
, ('CONT_DIF_N.active.enclosure' , 0.5)
, ('CONT_DIF_N.metal1.enclosure' , 0.5)
, ('CONT_DIF_P.minimum.side' , 1.0)
, ('CONT_DIF_P.pImplant.enclosure' , 1.0)
, ('CONT_DIF_P.active.enclosure' , 0.5)
, ('CONT_DIF_P.metal1.enclosure' , 0.5)
, ('CONT_POLY.minimum.width' , 1.0)
, ('CONT_POLY.poly.enclosure' , 0.5)
, ('CONT_POLY.metal1.enclosure' , 0.5)
# VIAs (i.e. Metal <--> Metal).
, ('VIA12.minimum.side' , 1.0)
, ('VIA12.metal1.enclosure' , 0.5)
, ('VIA12.metal2.enclosure' , 0.5)
, ('VIA23.minimum.side' , 1.0)
, ('VIA23.metal2.enclosure' , 0.5)
, ('VIA23.metal3.enclosure' , 0.5)
, ('VIA34.minimum.side' , 1.0)
, ('VIA34.metal3.enclosure' , 0.5)
, ('VIA34.metal4.enclosure' , 0.5)
, ('VIA45.minimum.side' , 1.0)
, ('VIA45.metal4.enclosure' , 0.5)
, ('VIA45.metal5.enclosure' , 0.5)
, ('VIA56.minimum.side' , 1.0)
, ('VIA56.metal5.enclosure' , 0.5)
, ('VIA56.metal6.enclosure' , 0.5)
, ('VIA67.minimum.side' , 1.0)
, ('VIA67.metal6.enclosure' , 0.5)
, ('VIA67.metal7.enclosure' , 0.5)
, ('VIA78.minimum.side' , 1.0)
, ('VIA78.metal7.enclosure' , 0.5)
, ('VIA78.metal8.enclosure' , 0.5)
# Blockages.
, ('BLOCKAGE1.minimum.width' , 1.0)
, ('BLOCKAGE1.blockage1.extention.cap' , 0.5)
, ('BLOCKAGE2.minimum.width' , 2.0)
, ('BLOCKAGE2.blockage2.extention.cap' , 0.5)
, ('BLOCKAGE3.minimum.width' , 2.0)
, ('BLOCKAGE3.blockage3.extention.cap' , 0.5)
, ('BLOCKAGE4.minimum.width' , 2.0)
, ('BLOCKAGE4.blockage4.extention.cap' , 0.5)
, ('BLOCKAGE5.minimum.width' , 2.0)
, ('BLOCKAGE5.blockage5.extention.cap' , 1.0)
, ('BLOCKAGE6.minimum.width' , 2.0)
, ('BLOCKAGE6.blockage6.extention.cap' , 1.0)
, ('BLOCKAGE7.minimum.width' , 2.0)
, ('BLOCKAGE7.blockage6.extention.cap' , 1.0)
, ('BLOCKAGE8.minimum.width' , 2.0)
, ('BLOCKAGE8.blockage6.extention.cap' , 1.0)
)