coriolis/bora/src
Jean-Paul Chaput 02777e127e Migration towards Python3, first stage: still based on C-Macros.
* New: Python/C++ API level:
  * Write a new C++/template wrapper to get rid of boost::python
  * The int & long Python type are now merged. So a C/C++ level,
    it became "PyLong_X" (remove "PyInt_X") and at Python code
    level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
  * Configuration is now integrated as a Hurricane component,
    makes use of the new C++/template wrapper.
  * vlsisapd is now defunct. Keep it in the source for now as
    some remaining non essential code may have to be ported in
    the future.
* Note: Python code (copy of the migration howto):
  * New print function syntax print().
  * Changed "dict.has_key(k)" for "k" in dict.
  * Changed "except Exception, e" for "except Exception as e".
  * The division "/" is now the floating point division, even if
    both operand are integers. So 3/2 now gives 1.5 and no longer 1.
    The integer division is now "//" : 1 = 3//2. So have to carefully
    review the code to update. Most of the time we want to use "//".
    We must never change to float for long that, in fact, represents
    DbU (exposed as Python int type).
  * execfile() must be replaced by exec(open("file").read()).
  * iter().__next__() becomes iter(x).__next__().
  * __getslice__() has been removed, integrated to __getitem__().
  * The formating used for str(type(o)) has changed, so In Stratus,
    have to update them ("<class 'MyClass'>" instead of "MyClass").
  * the "types" module no longer supply values for default types
    like str (types.StringType) or list (types.StringType).
    Must use "isinstance()" where they were occuring.
  * Remove the 'L' to indicate "long integer" (like "12L"), now
    all Python integer are long.
* Change in bootstrap:
  * Ported Coriolis builder (ccb) to Python3.
  * Ported Coriolis socInstaller.py to Python3.
  * Note: In PyQt4+Python3, QVariant no longer exists. Use None or
    directly convert using the python syntax: bool(x), int(x), ...
    By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
  * In order to compile user's must upgrade to my own rebuild of
    PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
    buffer of the H-Tree to the original signal (mainly: top clock).
      Strangely, it was only done when working in full chip mode.
2021-09-19 19:41:24 +02:00
..
attic Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
bora Improve symmetry management for analog designs. 2020-04-10 12:15:23 +02:00
BoraEngine.cpp Improve symmetry management for analog designs. 2020-04-10 12:15:23 +02:00
BoxSet.cpp Bug fixes in SlicingTree, bad refcount incrementation of BoxSet. 2019-11-22 18:29:09 +01:00
CMakeLists.txt Migration towards Python3, first stage: still based on C-Macros. 2021-09-19 19:41:24 +02:00
ChannelRouting.cpp Implementation of a red-black tree and an interval tree. 2018-11-07 23:48:43 +01:00
DSlicingNode.cpp Added Resistor support. Completed Capacitor & Resistor support in Bora. 2019-11-12 02:21:03 +01:00
GraphicBoraEngine.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
HSlicingNode.cpp Capacitor & resistor integration in the Slicing Tree. 2020-01-23 14:07:19 +01:00
HVSetState.cpp Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00
HVSlicingNode.cpp Improve symmetry management for analog designs. 2020-04-10 12:15:23 +02:00
NodeSets.cpp Capacitor support, at last. 2020-03-15 17:56:09 +01:00
ParameterRange.cpp First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
Pareto.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PyBora.cpp Migration towards Python3, first stage: still based on C-Macros. 2021-09-19 19:41:24 +02:00
PyBoraEngine.cpp Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00
PyDSlicingNode.cpp Migration towards Python3, first stage: still based on C-Macros. 2021-09-19 19:41:24 +02:00
PyGraphicBoraEngine.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PyHSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PyMatrixParameterRange.cpp Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00
PyParameterRange.cpp Clarify semantic of flatten Collections (walkthrough). 2020-03-10 12:10:53 +01:00
PyRHSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PyRVSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PySlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
PyStepParameterRange.cpp First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
PyVSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
RHSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
RHVSlicingNode.cpp Implementation of a red-black tree and an interval tree. 2018-11-07 23:48:43 +01:00
RVSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
SlicingDataModel.cpp Correct computation of H/W ratio in Bora (Igor Zivanovic). 2020-04-08 15:09:20 +02:00
SlicingDataWidget.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
SlicingNode.cpp Bug fix, reset Cell flags after unrouting an analog design. 2020-04-30 00:38:32 +02:00
SlicingPlotWidget.cpp Capacitor support, at last. 2020-03-15 17:56:09 +01:00
SlicingWidget.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
VSlicingNode.cpp Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
cpps Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00