344 lines
13 KiB
Python
344 lines
13 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./dpgen_Shrot.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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class DpgenShrot ( Model ) :
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## Interface ##
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###############
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def Interface ( self ) :
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global Slices
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global AndIndex
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self._nbit = self._param['nbit']
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Slices = ln2p ( self._nbit )
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self._op = SignalIn ( "op", 3 )
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self._shamt = SignalIn ( "shamt", Slices )
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self._i = SignalIn ( "i", self._nbit )
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self._o = SignalOut ( "o", self._nbit )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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## Netlist ##
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#############
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def Netlist ( self ) :
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global Slices
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AndIndex = 0
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# Signals
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MuxOutput = Signal ( "muxoutput", self._nbit * Slices + self._nbit )
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c0 = Signal ( "c0", Slices )
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c1 = Signal ( "c1", Slices )
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msb = Signal ( "msb", 1 )
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op2b = Signal ( "op2b", 1 )
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x = Signal ( "x", Slices * self._nbit )
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MuxInput0 = Signal ( "muxinput0" )
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MuxInput2 = Signal ( "muxinput2" )
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self.I = {}
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self.A3 = {}
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self.A = {}
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self.OA = {}
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self.O = {}
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self.M = {}
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self.Tie = {}
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# Arithmetic or input extension
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self.I[Slices] = Inst ( "inv_x2"
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, "i_%d" % Slices
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, map = { 'i' : self._op[2]
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, 'nq' : op2b
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.A3[Slices] = Inst ( "a3_x2"
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, "a3_%d" % Slices
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, map = { 'i0' : self._i[self._nbit-1]
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, 'i1' : op2b
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, 'i2' : self._op[1]
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, 'q' : msb
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Normalizing the input signals names
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for BitIndex in range ( self._nbit ) : self._i[BitIndex].Alias ( MuxOutput[BitIndex] )
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# Connecting the mux matrix
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for SliceIndex in range ( Slices ) :
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for BitIndex in range ( self._nbit ) :
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LeftIndex = BitIndex - ( 1 << SliceIndex )
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RightIndex = BitIndex + ( 1 << SliceIndex )
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if LeftIndex >= 0 :
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# MuxOutput[SliceIndex * self._nbit + LeftIndex].Alias ( MuxInput0 )
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MuxInput0 = MuxOutput[SliceIndex * self._nbit + LeftIndex]
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else :
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# x[AndIndex].Alias ( MuxInput0 )
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MuxInput0 = x[AndIndex]
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self.A[SliceIndex*self._nbit+BitIndex]= Inst ( "a2_x2"
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, "a_%d" % ( SliceIndex * self._nbit + BitIndex )
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, map = { 'i0' : self._op[2]
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, 'i1' : MuxOutput[SliceIndex * self._nbit + self._nbit + LeftIndex]
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, 'q' : x[AndIndex]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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AndIndex += 1
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if RightIndex < self._nbit:
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# MuxOutput[SliceIndex * self._nbit + RightIndex].Alias ( MuxInput2 )
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MuxInput2 = MuxOutput[SliceIndex * self._nbit + RightIndex]
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else :
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# x[AndIndex].Alias ( MuxInput2 )
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MuxInput2 = x[AndIndex]
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self.OA[SliceIndex*self._nbit+BitIndex] = Inst ( "oa22_x4"
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, "oa_%d" % ( SliceIndex * self._nbit + BitIndex )
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, map = { 'i0' : self._op[2]
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, 'i1' : MuxOutput[SliceIndex * self._nbit + RightIndex - self._nbit]
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, 'i2' : msb
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, 'q' : x[AndIndex]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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AndIndex += 1
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self.M[SliceIndex*self._nbit+BitIndex] = Inst ( "mx3_x2"
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, "m_%d" % ( SliceIndex * self._nbit + BitIndex )
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, map = { 'cmd0' : c0[SliceIndex]
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, 'cmd1' : c1[SliceIndex]
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, 'i0' : MuxInput0
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, 'i1' : MuxOutput[SliceIndex * self._nbit + BitIndex]
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, 'i2' : MuxInput2
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, 'q' : MuxOutput[( SliceIndex + 1 ) * self._nbit + BitIndex]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Normalizing the output signals names
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for BitIndex in range ( self._nbit ) :
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MuxOutput[Slices * self._nbit + BitIndex]._temp = 1
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self._o[BitIndex] <= MuxOutput[Slices * self._nbit + BitIndex]
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# Building the control signals
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for SliceIndex in range ( Slices ) :
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self.I[SliceIndex] = Inst ( "inv_x2"
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, "i_%d" % SliceIndex
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, map = { 'i' : self._shamt[SliceIndex]
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, 'nq' : c1[SliceIndex]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.O[SliceIndex]= Inst ( "o2_x2"
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, "o_%d" % SliceIndex
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, map = { 'i0' : c1[SliceIndex]
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, 'i1' : self._op[0]
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, 'q' : c0[SliceIndex]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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for SliceIndex in range ( Slices ) :
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for BitIndex in range ( self._nbit - 1, -1, -1 ) :
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l = 0
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r = 0
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LeftIndex = BitIndex - ( 1 << SliceIndex )
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RightIndex = BitIndex + ( 1 << SliceIndex )
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if RightIndex >= self._nbit : r = 1
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if LeftIndex < 0 : l = 1
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if l == 0 and r == 0 :
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self.Tie[SliceIndex*self._nbit+BitIndex] = Inst ( "tie_x0"
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, "tie_%d" % ( SliceIndex * self._nbit + BitIndex )
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, map = { 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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########## Layout ##########
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############################
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def Layout ( self ) :
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Slices = ln2p ( self._nbit )
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if self._nbit & 1 :
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sym = SYM_Y
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mys = NOSYM
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else :
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sym = NOSYM
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mys = SYM_Y
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BitIndex = self._nbit - 1
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SliceIndex = 0
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Place ( self.OA[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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, XY ( 0, 0 )
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)
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PlaceRight ( self.M[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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for SliceIndex in range ( 1, Slices ) :
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PlaceRight ( self.OA[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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PlaceRight ( self.M[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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for SliceIndex in range ( Slices ) :
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SetXYIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] )
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for BitIndex in range ( self._nbit - 1, -1, -1 ) :
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l = 0
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r = 0
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LeftIndex = BitIndex - ( 1 << SliceIndex )
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RightIndex = BitIndex + ( 1 << SliceIndex )
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if RightIndex >= self._nbit :
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if BitIndex != ( self._nbit - 1 ) :
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PlaceBottom ( self.OA[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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r = 1
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if LeftIndex < 0 :
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if r == 1 :
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PlaceRight ( self.A[SliceIndex * self._nbit + BitIndex ]
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, SYM ( BitIndex, sym, mys )
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)
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SetXYIns ( self.OA[SliceIndex * self._nbit + BitIndex] )
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else :
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PlaceBottom ( self.A[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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l = 1
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if l == 0 and r == 0 :
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PlaceBottom ( self.Tie[SliceIndex * self._nbit + BitIndex]
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, NOSYM
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)
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SetRefIns ( self.M[SliceIndex * self._nbit + self._nbit - 1] )
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for BitIndex in range ( self._nbit - 2, -1, -1 ) :
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PlaceBottom ( self.M[SliceIndex * self._nbit + BitIndex]
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, SYM ( BitIndex, sym, mys )
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)
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BitIndex = self._nbit # Upper line, this is necessary for the computation of the symetry
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SliceIndex = 0
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SetRefIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] )
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PlaceTop ( self.I[Slices]
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, SYM ( BitIndex, sym, mys )
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)
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PlaceRight ( self.A3[Slices]
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, SYM ( BitIndex, sym, mys )
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)
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for SliceIndex in range ( Slices ) :
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if SliceIndex > 0 :
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SetRefIns ( self.OA[SliceIndex * self._nbit + self._nbit - 1] )
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if SliceIndex == 0:
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PlaceRight ( self.I[SliceIndex]
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, SYM ( BitIndex, sym, mys )
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)
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else :
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PlaceTop ( self.I[SliceIndex]
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, SYM ( BitIndex, sym, mys )
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)
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PlaceRight ( self.O[SliceIndex]
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, SYM ( BitIndex, sym, mys )
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)
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## VBE ##
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#########
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def Vbe ( self ) :
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print "vbe of DpgenShrot not implemented"
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