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Jean-Paul Chaput ec3c22547a Bug fixes in the VST/VHDL driver coupled with BlifParser.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
    the external status of the former Net. When a Net::merge() is
    performed, we must keep track of whether the merged (destroyed)
    one was external and keep that information.
      Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
    virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
    search of the net name in *internal* aliases. Otherwise only the
    aliases tagged as *external* will be searched.
      It was a bug that, when looking for a Plug master net by name
    we got an homonymous internal net. In that case we must only
    look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
    unvectorize it, like when it is non-contiguous (we use the
    isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
    a flag UniquifyUpperCase to uniquify the names in uppercases.
    In case of a clash with the same name in lowercase.
      Prepend 'u' before all previously uppercased letter. For
    example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
      The Catalog flags is exported to Python for use by the blif2vst
    script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
    a new gate each time it is called instead of making just one for
    each Model. This way, if two outside nets are connected to one
    or zero they do not get merged (should work, but will be less
    clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
    master net in the instances models (by name), limit the search
    to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
    two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
    (i.e. components) with 'cmpt_' to avoid clash names with signals
    in VHDL.
2021-04-05 23:53:44 +02:00
anabatic Rewrite support for minimum area metal wires (stacked VIAs). 2021-04-05 00:01:54 +02:00
bootstrap Added utlity script bootstrap/resetDoc.sh to revert the generated doc. 2020-11-14 18:54:23 +01:00
bora Bug fix, reset Cell flags after unrouting an analog design. 2020-04-30 00:38:32 +02:00
coloquinte Add updators to modify cell sizes on the fly in Coloquinte. 2021-01-13 19:10:31 +01:00
crlcore Bug fixes in the VST/VHDL driver coupled with BlifParser. 2021-04-05 23:53:44 +02:00
cumulus Bug fixes in the VST/VHDL driver coupled with BlifParser. 2021-04-05 23:53:44 +02:00
documentation Updated PDFs, November 13, 2020 (15:02). 2020-11-13 15:02:56 +01:00
equinox Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
etesian Use the extention cap in Anabatic to ensure the METAL minimum area. 2021-04-01 08:46:02 +02:00
flute Added support for loading user defined global routing in Anabatic. 2020-09-30 11:55:39 +02:00
hurricane Bug fixes in the VST/VHDL driver coupled with BlifParser. 2021-04-05 23:53:44 +02:00
ispd Various typos correction (courtesy of G. Gouvine). 2019-07-30 13:13:57 +02:00
karakaze Correct Cell object detection while reading Oceane parameters. 2020-05-27 16:11:53 +02:00
katabatic Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
katana Rewrite support for minimum area metal wires (stacked VIAs). 2021-04-05 00:01:54 +02:00
kite Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
knik Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
lefdef Migrating doc from Sphinx towards Pelican. 2020-02-03 17:44:15 +01:00
mauka Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
metis Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
nimbus Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
oroshi Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
solstice Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
stratus1 Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
tutorial More PEP8 compliant Python code. Start rewrite Python/C++ wrappers. 2020-04-08 11:24:42 +02:00
unicorn Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
unittests Enhanced techno rule support. Inspector support bug fix. 2020-07-21 11:22:04 +02:00
vlsisapd Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
.gitignore Various bug corrections to pass the alliance-check-toolkit reference benchs. 2019-05-24 23:57:22 +02:00
Makefile Enabling the user to choose the devtoolset it needs. 2019-03-04 14:20:13 +01:00
README.rst Update doc link for the new Pelican generated one. 2020-02-10 13:38:06 +01:00

README.rst

.. -*- Mode: rst -*-


===============
Coriolis README
===============

Coriolis is a free database, placement tool and routing tool for VLSI design.


Purpose
=======

Coriolis provides several tools to perform the layout of VLSI circuits.  Its
main components are the Hurricane database, the Etesian placer and the Katana
router, but other tools can use the Hurricane database and the parsers
provided.

The user interface <cgt> is the prefered way to use Coriolis, but all
Coriolis tools are Python modules and thus scriptable.


Documentation
=============

The complete documentation is available here, both in pdf & html:

   ./documentation/output/html
   ./documentation/UsersGuide/UsersGuide.pdf

The documentation of the latest *stable* version is also
available online. It may be quite outdated from the *devel*
version.

    https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/latex/users-guide/UsersGuide.pdf


Building Coriolis
=================

To build Coriolis, ensure the following prerequisites are met:

* Python 2.7.
* cmake.
* boost.
* bison & flex.
* Qt 4 or 5.
* libxml2.
* RapidJSON
* A C++11 compliant compiler.

The build system relies on a fixed directory tree from the root
of the user currently building it. Thus first step is to get a clone of
the repository in the right place. Proceed as follow: ::

   ego@home:~$ mkdir -p ~/coriolis-2.x/src/support
   ego@home:~$ cd ~/coriolis-2.x/src/support
   ego@home:~$ git clone http://github.com/miloyip/rapidjson
   ego@home:~$ git checkout ec322005072076ef53984462fb4a1075c27c7dfd
   ego@home:~$ cd ~/coriolis-2.x/src
   ego@home:src$ git clone https://www-soc.lip6.fr/git/coriolis.git
   ego@home:src$ cd coriolis

If you want to use the *devel* branch: ::

    ego@home:coriolis$ git checkout devel

Then, build the tool: ::

    ego@home:coriolis$ make install

Coriolis gets installed at the root of the following tree: ::

    ~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/

Where ``<OS>`` is the name of your operating system and ``<DISTRIB>`` your
distribution.


Using Coriolis
==============

The Coriolis main interface can be launched with the command: ::

    ego@home:~: ~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/bin/coriolis

The ``coriolis`` script detects its location and setups the UNIX
environment appropriately, then lauches ``cgt`` (or *any* command, with the
``--run=<COMMAND>`` option).

Conversely, you can setup the current shell environement for Coriolis by 
using the helper ``coriolisEnv.py``, then run any Coriolis tool: ::

    ego@home:~$ eval `~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py`
    ego@home:~$ cgt -V