b9da9531a7
* Change: In CRL Core, the Alliance VHDL (vst) driver was renaming the
names of Cells, Instances and Nets into their VHDL conterparts.
But if we still work on the Cell after saving it, the Net renaming
will cause touble, especially when there are DeepNets. The name
of the DeepNet is generated from the Occurrence name with the dot
separator which is *not* a VHDL valid character for name, thus
after that the DeepNet name has changed it cannot be reassociated
with the Occurrence path. This was causing double-flattening issues.
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| cmake_modules | ||
| doc | ||
| etc | ||
| python | ||
| src | ||
| CMakeLists.txt | ||