676 lines
26 KiB
Python
676 lines
26 KiB
Python
#!/usr/bin/python
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# This file is part of the Coriolis Project.
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# Copyright (C) Laboratoire LIP6 - Departement ASIM
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# Universite Pierre et Marie Curie
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#
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# Main contributors :
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# Christophe Alexandre <Christophe.Alexandre@lip6.fr>
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# Sophie Belloeil <Sophie.Belloeil@lip6.fr>
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# Hugo Clement <Hugo.Clement@lip6.fr>
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# Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
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# Damien Dupuis <Damien.Dupuis@lip6.fr>
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# Christian Masson <Christian.Masson@lip6.fr>
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# Marek Sroka <Marek.Sroka@lip6.fr>
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#
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# The Coriolis Project is free software; you can redistribute it
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# and/or modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# The Coriolis Project is distributed in the hope that it will be
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# useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with the Coriolis Project; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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# USA
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#
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# License-Tag
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# Authors-Tag
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# ===================================================================
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#
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# x-----------------------------------------------------------------x
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# | |
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# | C O R I O L I S |
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# | S t r a t u s - Netlists/Layouts Description |
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# | |
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# | Author : Sophie BELLOEIL |
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# | E-mail : Sophie.Belloeil@asim.lip6.fr |
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# | =============================================================== |
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# | Py Module : "./dpgen_RAM.py" |
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# | *************************************************************** |
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# | U p d a t e s |
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# | |
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# x-----------------------------------------------------------------x
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from stratus import *
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class DpgenRam ( Model ) :
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## Interface ##
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###############
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def Interface ( self ) :
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global adrange
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self._nbit = self._param['nbit']
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self._nmot = self._param['nword']
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if self._nbit % 2 == 1 or self._nbit > 64 or self._nbit < 2 :
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print "Error in DpgenRam : the bit number must be even and no larger than 64\n"
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sys.exit ( 3 )
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if self._nmot % 8 != 0 or self._nmot > 256 or self._nmot < 32 :
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print "Error in instanciaton of DpgenRam"
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print "The word number (nword = %d) " % self._nmot, "must be multiple of 8, at least 32 and no larger than 256.\n"
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sys.exit ( 3 )
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if self._nmot > 128 : adrange = 8
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elif self._nmot > 64 : adrange = 7
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elif self._nmot > 32 : adrange = 6
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else : adrange = 5
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# Connecteurs externes
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self._ck = SignalIn ( "ck", 1 )
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self._w = SignalIn ( "w", 1 )
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self._selram = SignalIn ( "selram", 1 )
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self._ad = SignalIn ( "ad", adrange )
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self._datain = SignalIn ( "datain", self._nbit )
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self._dataout = TriState ( "dataout", self._nbit )
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self._vdd = VddIn ( "vdd" )
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self._vss = VssIn ( "vss" )
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## Netlist ##
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#############
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def Netlist ( self ) :
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# Signaux
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prech = Signal ( "prech", 1 )
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prechbis = Signal ( "prechbis", 1 )
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ad0x = Signal ( "ad0x", 1 )
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nad0x = Signal ( "nad0x", 1 )
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nsense = Signal ( "nsense", 1 )
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sensex = Signal ( "sensex", 1 )
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nsensex = Signal ( "nsensex", 1 )
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selramx = Signal ( "selramx", 1 )
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nwrite = Signal ( "nwrite", 1 )
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writex = Signal ( "writex", 1 )
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ndec00 = Signal ( "ndec00", 1 )
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ndec01 = Signal ( "ndec01", 1 )
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ndec10 = Signal ( "ndec10", 1 )
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ndec11 = Signal ( "ndec11", 1 )
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nck = Signal ( "nck", 1 )
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nckx = Signal ( "nckx", 1 )
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nckxbis = Signal ( "nckxbis", 1 )
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ad3x = Signal ( "ad3x", 1 )
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nad3x = Signal ( "nad3x", 1 )
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ad4x = Signal ( "ad4x", 1 )
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nad4x = Signal ( "nad4x", 1 )
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if adrange > 5 :
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ad5x = Signal ( "ad5x", 1 )
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nad5x = Signal ( "nad5x", 1 )
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if adrange > 6 :
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ad6x = Signal ( "ad6x", 1 )
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nad6x = Signal ( "nad6x", 1 )
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if adrange > 7 :
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ad7x = Signal ( "ad7x", 1 )
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nad7x = Signal ( "nad7x", 1 )
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bus0 = []
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nbus0 = []
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bus1 = []
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nbus1 = []
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sel = []
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nsel = []
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selx = []
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ndeca = []
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ndecb = []
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for i in range ( self._nbit ) :
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bus0 += [Signal ( "bus0_%d" % i, 1 )]
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nbus0 += [Signal ( "nbus0_%d" % i, 1 )]
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bus1 += [Signal ( "bus1_%d" % i, 1 )]
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nbus1 += [Signal ( "nbus1_%d" % i, 1 )]
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for i in range ( self._nmot ) :
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sel += [Signal ( "sel%d" % i, 1 )]
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nsel += [Signal ( "nsel%d" % i, 1 )]
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selx += [Signal ( "selx%d" % i, 1 )]
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ndeca += [Signal ( "ndeca%d" % i, 1 )]
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ndecb += [Signal ( "ndecb%d" % i, 1 )]
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# Lignes de bit
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self.Prech = {}
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self.Bit = {}
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self.Sense = {}
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bottom = 0
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for i in range ( self._nbit ) :
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self.Prech[i] = Inst ( "ram_prech_data"
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, "prech%d" % i
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, map = { 'prech' : prech
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, 'bit0' : bus0[i]
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, 'nbit0' : nbus0[i]
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, 'bit1' : bus1[i]
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, 'nbit1' : nbus1[i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.BitBis = {}
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for j in range ( 0, self._nmot, 4 ) :
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self.BitBis[j] = Inst ( "ram_mem_data"
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, "bit_%d_%d" % ( i, j )
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, map = { 'selxi' : selx[j]
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, 'bit0' : bus0[i]
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, 'nbit0' : nbus0[i]
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, 'bit1' : bus1[i]
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, 'nbit1' : nbus1[i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.BitBis[j+2] = Inst ( "ram_mem_data"
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, "bit_%d_%d" % ( i, j + 2 )
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, map = { 'selxi' : selx[j+2]
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, 'bit0' : bus0[i]
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, 'nbit0' : nbus0[i]
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, 'bit1' : bus1[i]
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, 'nbit1' : nbus1[i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Bit[i] = self.BitBis
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self.Sense[i] = Inst ( "ram_sense_data"
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, "sense%d" % i
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, map = { 'bit0' : bus0[i]
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, 'nbit0' : nbus0[i]
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, 'bit1' : bus1[i]
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, 'nbit1' : nbus1[i]
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, 'ad0x' : ad0x
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, 'nad0x' : nad0x
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, 'sensex' : sensex
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, 'nsensex' : nsensex
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, 'prechx' : prechbis
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, 'writex' : writex
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, 'din' : self._datain[i]
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, 'dout' : self._dataout[i]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Premiere ligne de la zone des buffers
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self.PrechBuf0 = Inst ( "ram_prech_buf0"
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, "prechbuf0"
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, map = { 'i' : nckx
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, 'nq' : prech
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf0 = {}
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for j in range ( 0, self._nmot, 4 ) :
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self.Buf0[j] = Inst ( "ram_mem_buf0"
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, "buf0_%d" % j
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, map = { 'i' : nsel[j]
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, 'nq' : selx[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf0[j+2] = Inst ( "ram_mem_buf0"
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, "buf0_%d" % ( j + 2 )
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, map = { 'i' : nsel[j+2]
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, 'nq' : selx[j+2]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.SenseBuf0 = Inst ( "ram_sense_buf0"
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, "sensebuf0"
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, map = { 'ad0' : self._ad[0]
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, 'nsense' : nsense
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, 'nckx' : nckxbis
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, 'nwrite' : nwrite
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, 'ad0x' : ad0x
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, 'nad0x' : nad0x
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, 'sensex' : sensex
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, 'nsensex' : nsensex
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, 'prech' : prechbis
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, 'writex' : writex
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Deuxieme ligne de la zone des buffers
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self.PrechBuf1 = Inst ( "ram_prech_buf1"
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, "prechbuf1"
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, map = { 'nck' : nck
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, 'nckx' : nckx
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf1 = {}
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for j in range ( 0, self._nmot, 4 ) :
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self.Buf1[j] = Inst ( "ram_mem_buf1"
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, "buf1_%d" % j
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, map = { 'seli' : sel[j]
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, 'nck' : nck
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, 'selramx' : selramx
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, 'nseli' : nsel[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Buf1[j+2] = Inst ( "ram_mem_buf1"
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, "buf1_%d" % ( j + 2 )
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, map = { 'seli' : sel[j+2]
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, 'nck' : nck
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, 'selramx' : selramx
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, 'nseli' : nsel[j+2]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.SenseBuf1 = Inst ( "ram_sense_buf1"
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, "sensebuf1"
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, map = { 'ck' : self._ck
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, 'selram' : self._selram
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, 'w' : self._w
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, 'nck' : nck
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, 'selramx' : selramx
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, 'nsense' : nsense
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, 'nwrite' : nwrite
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, 'nckx' : nckxbis
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Premiere ligne de la zone du decodeur
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self.PrechDecB = Inst ( "ram_prech_dec0"
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,"prechdecb"
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, map = { 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Dec = {}
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for j in range ( 0, self._nmot, 8 ) :
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self.Dec[j] = Inst ( "ram_mem_deci"
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, "dec_%d" % j
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, map = { 'i0' : ndeca[j]
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, 'i1' : ndecb[j]
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, 'i2' : ndec00
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, 'seli' : sel[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Dec[j+2] = Inst ( "ram_mem_deci"
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, "dec_%d" % ( j + 2 )
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, map = { 'i0' : ndeca[j]
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, 'i1' : ndecb[j]
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, 'i2' : ndec01
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, 'seli' : sel[j+2]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Dec[j+4] = Inst ( "ram_mem_deci"
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, "dec_%d" % ( j + 4 )
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, map = { 'i0' : ndeca[j]
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, 'i1' : ndecb[j]
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, 'i2' : ndec10
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, 'seli' : sel[j+4]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.Dec[j+6] = Inst ( "ram_mem_deci"
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, "dec_%d" % ( j + 6 )
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, map = { 'i0' : ndeca[j]
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, 'i1' : ndecb[j]
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, 'i2' : ndec11
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, 'seli' : sel[j+6]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.SenseDecAd12 = Inst ( "ram_sense_decad12"
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, "sensedecad12"
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, map = { 'ad1' : self._ad[1]
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, 'ad2' : self._ad[2]
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, 'ndec00' : ndec00
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, 'ndec01' : ndec01
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, 'ndec10' : ndec10
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, 'ndec11' : ndec11
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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# Deuxieme ligne de la zone du decodeur
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if adrange == 8 : # adresse sur 8 bits : on decode 5 bits
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self.PrechDecU = Inst ( "ram_prech_dec0"
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, "prechdecu"
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, map = { 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.MemDec = {}
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for j in range ( 0, self._nmot, 8 ) :
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thisMap = { 'ndeca' : ndeca[j]
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, 'ndecb' : ndecb[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x
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else : thisMap['i0'] = ad3x
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if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x
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else : thisMap['i1'] = ad4x
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if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x
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else : thisMap['i2'] = ad5x
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if ( j >> 6 ) % 2 == 0 : thisMap['i3'] = nad6x
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else : thisMap['i3'] = ad6x
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if ( j >> 7 ) % 2 == 0 : thisMap['i4'] = nad7x
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else : thisMap['i4'] = ad7x
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self.MemDec[j] = Inst ( "ram_mem_dec5"
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, "memdec%d" % j
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, map = thisMap
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)
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self.SenseDecAd = Inst ( "ram_sense_decad5"
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, "sensedecad"
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, map = { 'ad3' : self._ad[3]
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, 'ad4' : self._ad[4]
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, 'ad5' : self._ad[5]
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, 'ad6' : self._ad[6]
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, 'ad7' : self._ad[7]
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, 'ad3x' : ad3x
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, 'nad3x' : nad3x
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, 'ad4x' : ad4x
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, 'nad4x' : nad4x
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, 'ad5x' : ad5x
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, 'nad5x' : nad5x
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, 'ad6x' : ad6x
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, 'nad6x' : nad6x
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, 'ad7x' : ad7x
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, 'nad7x' : nad7x
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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if adrange == 7 : # adresse sur 7 bits : on decode 4 bits
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self.PrechDecU = Inst ( "ram_prech_dec0"
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, "prechdecu"
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, map = { 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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)
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self.MemDec = {}
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for j in range ( 0, self._nmot, 8 ) :
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thisMap = { 'ndeca' : ndeca[j]
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, 'ndecb' : ndecb[j]
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, 'vdd' : self._vdd
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, 'vss' : self._vss
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}
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if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x
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else : thisMap['i0'] = ad3x
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if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x
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else : thisMap['i1'] = ad4x
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if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x
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else : thisMap['i2'] = ad5x
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if ( j >> 6 ) % 2 == 0 : thisMap['i3'] = nad6x
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else : thisMap['i3'] = ad6x
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self.MemDec[j] = Inst ( "ram_mem_dec4"
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, "memdec%d" % j
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, map = thisMap
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)
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self.SenseDecAd = Inst ( "ram_sense_decad4"
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, "sensedecad"
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, map = { 'ad3' : self._ad[3]
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, 'ad4' : self._ad[4]
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, 'ad5' : self._ad[5]
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, 'ad6' : self._ad[6]
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, 'ad3x' : ad3x
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, 'nad3x' : nad3x
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, 'ad4x' : ad4x
|
|
, 'nad4x' : nad4x
|
|
, 'ad5x' : ad5x
|
|
, 'nad5x' : nad5x
|
|
, 'ad6x' : ad6x
|
|
, 'nad6x' : nad6x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 6 : # adresse sur 6 bits : on decode 3 bits
|
|
self.PrechDecU = Inst ( "ram_prech_dec0"
|
|
, "prechdecu"
|
|
, map = { 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.MemDec = {}
|
|
for j in range ( 0, self._nmot, 8 ) :
|
|
thisMap = { 'ndeca' : ndeca[j]
|
|
, 'ndecb' : ndecb[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x
|
|
else : thisMap['i0'] = ad3x
|
|
|
|
if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x
|
|
else : thisMap['i1'] = ad4x
|
|
|
|
if ( j >> 5 ) % 2 == 0 : thisMap['i2'] = nad5x
|
|
else : thisMap['i2'] = ad5x
|
|
|
|
self.MemDec[j] = Inst ( "ram_mem_dec3"
|
|
, "memdec%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.SenseDecAd = Inst ( "ram_sense_decad3"
|
|
, "sensedecad"
|
|
, map = { 'ad3' : self._ad[3]
|
|
, 'ad4' : self._ad[4]
|
|
, 'ad5' : self._ad[5]
|
|
, 'ad3x' : ad3x
|
|
, 'nad3x' : nad3x
|
|
, 'ad4x' : ad4x
|
|
, 'nad4x' : nad4x
|
|
, 'ad5x' : ad5x
|
|
, 'nad5x' : nad5x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
if adrange == 5 : # adresse sur 5 bits : on decode 2 bits
|
|
self.PrechDecU = Inst ( "ram_prech_dec0"
|
|
, "prechdecu"
|
|
, map = { 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
self.MemDec = {}
|
|
for j in range ( 0, self._nmot, 8 ) :
|
|
thisMap = { 'ndeca' : ndeca[j]
|
|
, 'ndecb' : ndecb[j]
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
|
|
if ( j >> 3 ) % 2 == 0 : thisMap['i0'] = nad3x
|
|
else : thisMap['i0'] = ad3x
|
|
|
|
if ( j >> 4 ) % 2 == 0 : thisMap['i1'] = nad4x
|
|
else : thisMap['i1'] = ad4x
|
|
|
|
self.MemDec[j] = Inst ( "ram_mem_dec2"
|
|
, "memdec%d" % j
|
|
, map = thisMap
|
|
)
|
|
|
|
self.SenseDecAd = Inst ( "ram_sense_decad2"
|
|
, "sensedecad"
|
|
, map = { 'ad3' : self._ad[3]
|
|
, 'ad4' : self._ad[4]
|
|
, 'ad3x' : ad3x
|
|
, 'nad3x' : nad3x
|
|
, 'ad4x' : ad4x
|
|
, 'nad4x' : nad4x
|
|
, 'vdd' : self._vdd
|
|
, 'vss' : self._vss
|
|
}
|
|
)
|
|
|
|
|
|
########## Layout ##########
|
|
############################
|
|
def Layout ( self ) :
|
|
|
|
HCELL = 50
|
|
|
|
# Lignes de bit
|
|
bottom = 0
|
|
|
|
for i in range ( self._nbit ) :
|
|
if i % 2 : # lignes impaires
|
|
sym1 = SYM_Y
|
|
sym2 = SYMXY
|
|
else : # lignes paires
|
|
sym1 = NOSYM
|
|
sym2 = SYM_X
|
|
|
|
Place ( self.Prech[i], sym1, XY ( 0, bottom + i * HCELL ) )
|
|
|
|
for j in range ( 0, self._nmot, 4 ) :
|
|
PlaceRight ( self.Bit[i][j], sym2 )
|
|
PlaceRight ( self.Bit[i][j+2], sym1 )
|
|
|
|
PlaceRight ( self.Sense[i], sym1 )
|
|
|
|
# Premiere ligne de la zone des buffers
|
|
bottom = self._nbit * HCELL
|
|
|
|
Place ( self.PrechBuf0, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( 0, self._nmot, 4 ) :
|
|
PlaceRight ( self.Buf0[j], SYM_X )
|
|
PlaceRight ( self.Buf0[j+2], NOSYM )
|
|
|
|
PlaceRight ( self.SenseBuf0, NOSYM )
|
|
|
|
# Deuxieme ligne de la zone des buffers
|
|
bottom = ( self._nbit + 1 ) * HCELL
|
|
|
|
Place ( self.PrechBuf1, SYM_Y, XY ( 0, bottom ) )
|
|
|
|
for j in range ( 0, self._nmot, 4 ) :
|
|
PlaceRight ( self.Buf1[j], SYMXY )
|
|
PlaceRight ( self.Buf1[j+2], SYM_Y )
|
|
|
|
PlaceRight ( self.SenseBuf1, SYM_Y )
|
|
|
|
# Premiere ligne de la zone du decodeur
|
|
bottom = ( self._nbit + 2 ) * HCELL
|
|
|
|
Place ( self.PrechDecB, NOSYM, XY ( 0, bottom ) )
|
|
|
|
for j in range ( 0, self._nmot, 8 ) :
|
|
PlaceRight ( self.Dec[j], SYM_X )
|
|
PlaceRight ( self.Dec[j+2], NOSYM )
|
|
PlaceRight ( self.Dec[j+4], SYM_X )
|
|
PlaceRight ( self.Dec[j+6], NOSYM )
|
|
|
|
PlaceRight ( self.SenseDecAd12, NOSYM )
|
|
|
|
# Deuxieme ligne de la zone du decodeur
|
|
bottom = ( self._nbit + 3 ) * HCELL
|
|
|
|
if adrange == 8 : # adresse sur 8 bits : on decode 5 bits
|
|
Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y )
|
|
PlaceRight ( self.SenseDecAd, SYM_Y )
|
|
|
|
if adrange == 7 : # adresse sur 7 bits : on decode 4 bits
|
|
Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y )
|
|
PlaceRight ( self.SenseDecAd, SYM_Y )
|
|
|
|
if adrange == 6 : # adresse sur 6 bits : on decode 3 bits
|
|
Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y )
|
|
PlaceRight ( self.SenseDecAd, SYM_Y )
|
|
|
|
if adrange == 5 : # adresse sur 5 bits : on decode 2 bits
|
|
Place ( self.PrechDecU, SYM_Y, XY ( 0, bottom ) )
|
|
for j in range ( 0, self._nmot, 8 ) : PlaceRight ( self.MemDec[j], SYM_Y )
|
|
PlaceRight ( self.SenseDecAd, SYM_Y )
|
|
|
|
|
|
## VBE ##
|
|
#########
|
|
def Vbe () :
|
|
print "RAM behavior not yet implemented"
|