coriolis/crlcore/etc/common
EricLaoGitHub 06d818695f Dijkstra can handle mixedsignal wires. 2017-06-21 18:02:37 +02:00
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display.conf Dijkstra can handle mixedsignal wires. 2017-06-21 18:02:37 +02:00
etesian.conf Python Script launcher extended to accomodate Chams. 2015-03-17 16:31:24 +01:00
hMetis.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
kite.conf Enable the display of GCells as a density map (and not boundaries). 2016-09-10 18:49:48 +02:00
mauka.conf Buffer cell configuration in ClockTree. More config parameters in Chip. 2014-09-02 11:17:47 +02:00
misc.conf In CellPrinter, adds the DPI and the Orientation as config. parameters. 2017-03-15 17:59:00 +01:00
nimbus.conf Bug in Python proxy deallocation. Update to latest Coloquinte. 2015-02-13 23:38:55 +01:00
patterns.conf Added METCAP layer, for MIM capacitors. 2016-03-06 12:40:23 +01:00
stratus1.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
technology.conf In Anabatic, check if there is at least one METAL1 in singleGCell(). 2016-12-15 19:25:05 +01:00