coriolis/crlcore/etc
Jean-Paul Chaput 8ad910301d In CRLcore, new gauge "msxlib4" for compliance with AMS 350nm (symbolic).
* New: In CRL/etc/symbolic/cmos45/kite.conf, new gauge "msxlib4" for both
    routing and cells. Have only 4 metal layers but with all the same pitches
    and width. Differs from the 45nm compliant where pitches double starting
    from METAL4.
* New: In CRL/etc/symbolic/cmos45/plugins.conf, adjust default parameters for
    the clock tree plugin so they are identical to the one of "cmos" (scaling).
* Change: In CRL/python/helpers/io.py, in catch(), do not set up the script
    path here as it is non-informative.
2019-05-29 13:16:01 +02:00
..
45 First step in supporting ISPD18 detailed routing benchmarks. 2019-03-29 11:07:55 +01:00
180/scn6m_deep_09 Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
common Correct CellWidget & CellPrinter to be really WYSIWYG. 2019-02-20 18:24:43 +01:00
symbolic In CRLcore, new gauge "msxlib4" for compliance with AMS 350nm (symbolic). 2019-05-29 13:16:01 +02:00
CMakeLists.txt Reorganisation of technology configuration files. 2017-11-17 11:10:32 +01:00
techno.conf Reorganisation of technology configuration files. 2017-11-17 11:10:32 +01:00