coriolis/crlcore/etc
Jean-Paul Chaput bbcf14eb5a First step in supporting ISPD18 detailed routing benchmarks.
* Change: In CRL::DefImport, added callback to read the DEF UNITS statement
    and perform a correct length conversion. Previously set to read pseudo
    lambdas in hundredth of microns.
      Added DefParser::getLefCell() to lookup master cells in the LEF
    libraries before looking in the Alliance ones (rooted under "LEF"
    library).
* Change: In CRL::LefParser::_pinPostProcess(), when no segment suitable
    for terminal connexion is found, add all of them. This is a quick hack
    and an a correct policy that match all techno must be implemeneted.
* New: In CRL::pyCRL, add a Python wrapper for DefImport.
* New: In CRL/etc/45/ispd18/ added configuration files for the "real"
    technology used by the ISPD18 45nm design benchmarks.
2019-03-29 11:07:55 +01:00
..
45 First step in supporting ISPD18 detailed routing benchmarks. 2019-03-29 11:07:55 +01:00
180/scn6m_deep_09 Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
common Correct CellWidget & CellPrinter to be really WYSIWYG. 2019-02-20 18:24:43 +01:00
symbolic Reorganisation of menus in a more clear way. 2019-03-05 23:23:14 +01:00
CMakeLists.txt Reorganisation of technology configuration files. 2017-11-17 11:10:32 +01:00
techno.conf Reorganisation of technology configuration files. 2017-11-17 11:10:32 +01:00