* Change: In CRL Core, etc/, update the configuration files of real
technologies. Mostly for FreePDK 45. This work is also done for
AMS c35b4 (350nm) but in a private (SoC) git repository.
Added a new parameter 'lefImport.minTerminalwidth' for the
minimum size (width) of a metal1 terminal in standard cells.
Corrected bug of the minimum trace level which must be
initialized to a great value and *not* zero;
* Change: In CRL Core, BlifParser, detect when there is no tie low
or tie high defined, issue an error (connexion left open) but
continue.
* New: In CRL::RoutingLayerGauge, new overlad of getTrackPosition()
with the parameter set of getTrackIndex(). Used to know if a
terminal is on-grid or not.
* New: In CRL::LefImport, smarter management of metal1 pins. Adds a
_pinPostProcess() function to select the external components
among the various shapes. If the gauge is VH, all the pin rectangles
are translateds into vertical segments (even if the metal1 gauge
says the tracks are horizontals).
The _pinPostProcess() function adds as external components of
a net, only the segments of a sufficent width as given in
'lefImport.minTerminalWidth' and that are on-grid.
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