coriolis/crlcore
Jean-Paul Chaput b23f620c5d The VST driver may suppress linkage type.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
    undefined directions are typed "linkage". This may not be compatible
    with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
   the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
    of the "linkage" type.
2020-06-24 23:27:21 +02:00
..
cmake_modules Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
doc Full update of the generated documentation. 2020-04-27 14:14:03 +02:00
etc Bug fix, restore the FreePDK 45 (real) support. 2020-04-27 10:34:19 +02:00
python Add forgotten asDouble() method to the Parameter interface. 2020-06-16 21:33:33 +02:00
src The VST driver may suppress linkage type. 2020-06-24 23:27:21 +02:00
CMakeLists.txt Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00