77 lines
3.0 KiB
TeX
77 lines
3.0 KiB
TeX
\begin{itemize}
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\item \textbf{Name} : DpgenAdsb2f -- Adder/Substractor Macro-Generator
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\item \textbf{Synopsys} :
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\begin{verbatim}
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Generate ( 'DpgenAdsb2f', modelname
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, param = { 'nbit' : n
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, 'physical' : True
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, 'behavioral' : True
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}
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)
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\end{verbatim}
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\item \textbf{Description} : Generates a \verb-n- bits adder/substractor named \verb-modelname-.
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\item \textbf{Terminal Names} :
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\begin{itemize}
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\item \textbf{i0} : First operand (input, \verb-n- bits)
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\item \textbf{i1} : Second operand (input, \verb-n- bits)
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\item \textbf{q} : Output operand (ouput, \verb-n- bits)
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\item \textbf{add\_sub} : Select addition or substraction (input, 1 bit)
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\item \textbf{c31} : Sarry out. In unsigned mode, this is the overflow (output, 1 bit)
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\item \textbf{c30} : Used to compute overflow in signed mode : \verb-overflow = c31 xor c30- (output, 1 bit)
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\item \textbf{vdd} : power
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\item \textbf{vss} : ground
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\end{itemize}
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\item \textbf{Parameters} : Parameters are given in the map \verb-param-.
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\begin{itemize}
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\item \textbf{nbit} (mandatory) : Defines the size of the generator
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\item \textbf{physical} (optional, default value : False) : In order to generate a layout
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\item \textbf{behavioral} (optional, default value : False) : In order to generate a behavior
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\end{itemize}
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\item \textbf{How it works} :
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\begin{itemize}
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\item If the \verb-add_sub- signal is set to \verb-zero-, an addition is performed, otherwise it's a substraction.
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\item Operation can be either signed or unsigned. In unsigned mode \verb-c31- is the overflow ; in signed mode you have to compute overflow by \emph{XORing} \verb-c31- and \verb-c30-
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\end{itemize}
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% \item \textbf{Behavior} :
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%\begin{verbatim}
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%\end{verbatim}
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\item \textbf{Example} :
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\begin{verbatim}
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from stratus import *
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class inst_ADSB2F ( Model ) :
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def Interface ( self ) :
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self.in1 = SignalIn ( "in1", 8 )
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self.in2 = SignalIn ( "in2", 8 )
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self.out = SignalOut ( "o", 8 )
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self.as = SignalIn ( "as", 1 )
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self.c0 = SignalOut ( "c0", 1 )
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self.c1 = SignalOut ( "c1", 1 )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Generate ( 'DpgenAdsb2f', 'adder_8'
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, param = { 'nbit' : 8
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, 'physical' : True
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}
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)
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self.I = Inst ( 'adder_8', 'inst'
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, map = { 'i0' : self.in1
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, 'i1' : self.in2
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, 'add_sub' : self.as
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, 'q' : self.out
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, 'c30' : self.c0
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, 'c31' : self.c1
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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def Layout ( self ) :
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Place ( self.I, NOSYM, Ref(0, 0) )
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\end{verbatim}
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\end{itemize}
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