612 lines
11 KiB
Plaintext
612 lines
11 KiB
Plaintext
entity accu is
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port (
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cke : in bit;
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i : in bit_vector(2 downto 0);
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alu_out : in bit_vector(3 downto 0);
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q0_from : in bit;
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q3_from : in bit;
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q0_to : out mux_bit bus;
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q3_to : out mux_bit bus;
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accu : inout bit_vector(3 downto 0);
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vdd : in bit;
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vss : in bit
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);
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end accu;
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architecture structural of accu is
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Component o2_x2
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component no2_x1
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port (
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i0 : in bit;
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i1 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component inv_x2
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port (
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i : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component ao22_x2
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component an12_x1
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component nao22_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component na2_x1
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port (
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i0 : in bit;
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i1 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component on12_x1
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port (
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i0 : in bit;
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i1 : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component na3_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component sff1_x4
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port (
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ck : in bit;
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i : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component buf_x2
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port (
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i : in bit;
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q : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component no3_x1
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port (
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i0 : in bit;
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i1 : in bit;
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i2 : in bit;
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nq : out bit;
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vdd : in bit;
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vss : in bit
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);
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end component;
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Component ts_x8
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port (
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cmd : in bit;
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i : in bit;
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q : out mux_bit bus;
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vdd : in bit;
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vss : in bit
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);
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end component;
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signal not_i : bit_vector( 2 downto 1);
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signal rtlalc_0 : bit_vector( 3 downto 0);
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signal on12_x1_sig : bit;
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signal on12_x1_6_sig : bit;
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signal on12_x1_5_sig : bit;
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signal on12_x1_4_sig : bit;
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signal on12_x1_3_sig : bit;
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signal on12_x1_2_sig : bit;
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signal not_aux2 : bit;
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signal no3_x1_sig : bit;
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signal no3_x1_2_sig : bit;
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signal nao22_x1_sig : bit;
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signal nao22_x1_4_sig : bit;
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signal nao22_x1_3_sig : bit;
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signal nao22_x1_2_sig : bit;
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signal na3_x1_sig : bit;
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signal na3_x1_8_sig : bit;
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signal na3_x1_7_sig : bit;
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signal na3_x1_6_sig : bit;
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signal na3_x1_5_sig : bit;
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signal na3_x1_4_sig : bit;
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signal na3_x1_3_sig : bit;
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signal na3_x1_2_sig : bit;
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signal na2_x1_sig : bit;
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signal na2_x1_4_sig : bit;
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signal na2_x1_3_sig : bit;
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signal na2_x1_2_sig : bit;
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signal inv_x2_sig : bit;
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signal inv_x2_2_sig : bit;
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signal aux3 : bit;
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signal aux1 : bit;
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signal aux0 : bit;
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signal ao22_x2_sig : bit;
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signal ao22_x2_2_sig : bit;
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signal an12_x1_sig : bit;
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signal an12_x1_2_sig : bit;
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begin
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not_aux2_ins : o2_x2
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port map (
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i0 => i(0),
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i1 => not_i(1),
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q => not_aux2,
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vdd => vdd,
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vss => vss
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);
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not_i_2_ins : inv_x2
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port map (
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i => i(2),
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nq => not_i(2),
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vdd => vdd,
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vss => vss
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);
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not_i_1_ins : inv_x2
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port map (
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i => i(1),
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nq => not_i(1),
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vdd => vdd,
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vss => vss
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);
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aux3_ins : no2_x1
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port map (
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i0 => i(1),
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i1 => i(0),
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nq => aux3,
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vdd => vdd,
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vss => vss
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);
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aux1_ins : on12_x1
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port map (
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i0 => i(2),
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i1 => accu(2),
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q => aux1,
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vdd => vdd,
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vss => vss
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);
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aux0_ins : on12_x1
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port map (
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i0 => i(2),
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i1 => accu(1),
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q => aux0,
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vdd => vdd,
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vss => vss
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);
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inv_x2_ins : inv_x2
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port map (
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i => not_aux2,
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nq => inv_x2_sig,
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vdd => vdd,
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vss => vss
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);
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ao22_x2_ins : ao22_x2
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port map (
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i0 => not_i(2),
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i1 => q0_from,
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i2 => inv_x2_sig,
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q => ao22_x2_sig,
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vdd => vdd,
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vss => vss
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);
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nao22_x1_ins : nao22_x1
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port map (
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i0 => rtlalc_0(0),
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i1 => i(2),
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i2 => ao22_x2_sig,
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nq => nao22_x1_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_ins : na2_x1
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port map (
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i0 => i(0),
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i1 => rtlalc_0(0),
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nq => na2_x1_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_ins : on12_x1
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port map (
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i0 => not_i(2),
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i1 => alu_out(0),
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q => on12_x1_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_2_ins : na3_x1
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port map (
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i0 => aux3,
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i1 => on12_x1_sig,
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i2 => aux0,
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nq => na3_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_ins : na3_x1
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port map (
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i0 => na3_x1_2_sig,
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i1 => na2_x1_sig,
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i2 => nao22_x1_sig,
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nq => na3_x1_sig,
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vdd => vdd,
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vss => vss
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);
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rtlalc_0_0_ins : sff1_x4
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port map (
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ck => cke,
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i => na3_x1_sig,
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q => rtlalc_0(0),
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vdd => vdd,
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vss => vss
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);
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inv_x2_2_ins : inv_x2
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port map (
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i => not_aux2,
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nq => inv_x2_2_sig,
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vdd => vdd,
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vss => vss
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);
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ao22_x2_2_ins : ao22_x2
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port map (
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i0 => not_i(2),
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i1 => accu(0),
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i2 => inv_x2_2_sig,
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q => ao22_x2_2_sig,
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vdd => vdd,
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vss => vss
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);
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nao22_x1_2_ins : nao22_x1
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port map (
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i0 => rtlalc_0(1),
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i1 => i(2),
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i2 => ao22_x2_2_sig,
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nq => nao22_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_2_ins : na2_x1
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port map (
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i0 => i(0),
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i1 => rtlalc_0(1),
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nq => na2_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_2_ins : on12_x1
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port map (
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i0 => not_i(2),
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i1 => alu_out(1),
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q => on12_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_4_ins : na3_x1
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port map (
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i0 => aux3,
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i1 => on12_x1_2_sig,
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i2 => aux1,
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nq => na3_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_3_ins : na3_x1
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port map (
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i0 => na3_x1_4_sig,
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i1 => na2_x1_2_sig,
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i2 => nao22_x1_2_sig,
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nq => na3_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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rtlalc_0_1_ins : sff1_x4
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port map (
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ck => cke,
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i => na3_x1_3_sig,
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q => rtlalc_0(1),
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vdd => vdd,
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vss => vss
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);
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an12_x1_ins : an12_x1
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port map (
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i0 => not_aux2,
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i1 => aux0,
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q => an12_x1_sig,
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vdd => vdd,
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vss => vss
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);
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nao22_x1_3_ins : nao22_x1
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port map (
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i0 => rtlalc_0(2),
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i1 => i(2),
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i2 => an12_x1_sig,
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nq => nao22_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_3_ins : na2_x1
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port map (
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i0 => i(0),
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i1 => rtlalc_0(2),
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nq => na2_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_3_ins : on12_x1
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port map (
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i0 => i(2),
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i1 => accu(3),
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q => on12_x1_3_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_4_ins : on12_x1
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port map (
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i0 => not_i(2),
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i1 => alu_out(2),
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q => on12_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_6_ins : na3_x1
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port map (
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i0 => on12_x1_4_sig,
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i1 => on12_x1_3_sig,
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i2 => aux3,
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nq => na3_x1_6_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_5_ins : na3_x1
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port map (
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i0 => na3_x1_6_sig,
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i1 => na2_x1_3_sig,
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i2 => nao22_x1_3_sig,
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nq => na3_x1_5_sig,
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vdd => vdd,
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vss => vss
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);
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rtlalc_0_2_ins : sff1_x4
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port map (
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ck => cke,
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i => na3_x1_5_sig,
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q => rtlalc_0(2),
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vdd => vdd,
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vss => vss
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);
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an12_x1_2_ins : an12_x1
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port map (
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i0 => not_aux2,
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i1 => aux1,
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q => an12_x1_2_sig,
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vdd => vdd,
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vss => vss
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);
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nao22_x1_4_ins : nao22_x1
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port map (
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i0 => rtlalc_0(3),
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i1 => i(2),
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i2 => an12_x1_2_sig,
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nq => nao22_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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na2_x1_4_ins : na2_x1
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port map (
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i0 => i(0),
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i1 => rtlalc_0(3),
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nq => na2_x1_4_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_5_ins : on12_x1
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port map (
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i0 => i(2),
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i1 => q3_from,
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q => on12_x1_5_sig,
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vdd => vdd,
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vss => vss
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);
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on12_x1_6_ins : on12_x1
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port map (
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i0 => not_i(2),
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i1 => alu_out(3),
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q => on12_x1_6_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_8_ins : na3_x1
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port map (
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i0 => on12_x1_6_sig,
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i1 => on12_x1_5_sig,
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i2 => aux3,
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nq => na3_x1_8_sig,
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vdd => vdd,
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vss => vss
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);
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na3_x1_7_ins : na3_x1
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port map (
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i0 => na3_x1_8_sig,
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i1 => na2_x1_4_sig,
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i2 => nao22_x1_4_sig,
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nq => na3_x1_7_sig,
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vdd => vdd,
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vss => vss
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);
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rtlalc_0_3_ins : sff1_x4
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port map (
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ck => cke,
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i => na3_x1_7_sig,
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q => rtlalc_0(3),
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vdd => vdd,
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vss => vss
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);
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accu_0_ins : buf_x2
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port map (
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i => rtlalc_0(0),
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q => accu(0),
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vdd => vdd,
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vss => vss
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);
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accu_1_ins : buf_x2
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port map (
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i => rtlalc_0(1),
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q => accu(1),
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vdd => vdd,
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vss => vss
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);
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accu_2_ins : buf_x2
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port map (
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i => rtlalc_0(2),
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q => accu(2),
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vdd => vdd,
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vss => vss
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);
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accu_3_ins : buf_x2
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port map (
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i => rtlalc_0(3),
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q => accu(3),
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vdd => vdd,
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vss => vss
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);
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no3_x1_ins : no3_x1
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port map (
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i0 => not_i(1),
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i1 => not_i(2),
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i2 => i(0),
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nq => no3_x1_sig,
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vdd => vdd,
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vss => vss
|
|
);
|
|
|
|
q3_to_ins : ts_x8
|
|
port map (
|
|
cmd => no3_x1_sig,
|
|
i => alu_out(3),
|
|
q => q3_to,
|
|
vdd => vdd,
|
|
vss => vss
|
|
);
|
|
|
|
no3_x1_2_ins : no3_x1
|
|
port map (
|
|
i0 => i(1),
|
|
i1 => not_i(2),
|
|
i2 => i(0),
|
|
nq => no3_x1_2_sig,
|
|
vdd => vdd,
|
|
vss => vss
|
|
);
|
|
|
|
q0_to_ins : ts_x8
|
|
port map (
|
|
cmd => no3_x1_2_sig,
|
|
i => alu_out(0),
|
|
q => q0_to,
|
|
vdd => vdd,
|
|
vss => vss
|
|
);
|
|
|
|
|
|
end structural;
|