Jean-Paul Chaput 2ba7bb4fca Better Verilog/VHDL name mixing in the Blif parser. ... * Change: In Model::connectSubckts(), when trying to lookup the Hurricane Net from it's Blif name, try first as a VHDL one then after a Verilog to VHDL translation. Especially useful for bits of vectorized names ("signal[X]" --> "signal(X)").		2021-02-01 16:18:25 +01:00
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cmake_modules	Compliance with Debian 10 Buster.	2020-03-19 18:18:35 +01:00
doc	Documentation cleanup & rebuild.	2020-11-12 14:22:31 +01:00
etc	In LibreSOCIO, allow to choose between complete/abstract layout.	2020-12-07 16:41:09 +01:00
python	Fix I/O Pad ring 45 degree corners where off the foundry grid.	2020-12-09 00:05:52 +01:00
src	Better Verilog/VHDL name mixing in the Blif parser.	2021-02-01 16:18:25 +01:00
CMakeLists.txt	Groudwork for routing density driven placement. Compliance with clang 5.0.1.	2019-12-09 01:57:44 +01:00