coriolis/crlcore
Jean-Paul Chaput 82dc58bf8e Redesign of I/O pads and Corona support to mix real and symbolic.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
    longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
    Must normalize Pin behavior between Alliance & Hurricane as in
    Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
    global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
    now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
    the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
    we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
    support:
    * Uncouple pad I/O ring whith real cells (foundry) from a symbolic
      core. A new intermediate level "corona" is introduced to handle
      the real/symbolic transition.
    * Ability to explicitly setup position of the pads on the chip side
      in case of uneven distribution.
    * Enable clock tree to be build with 3 metal only (M2 to M4) instead
      of (M2 to M5).
2019-05-10 11:58:05 +02:00
..
cmake_modules New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00
doc Analog integration part II. Analog place & route (slicing tree). 2018-10-18 18:10:01 +02:00
etc Redesign of I/O pads and Corona support to mix real and symbolic. 2019-05-10 11:58:05 +02:00
python Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
src Redesign of I/O pads and Corona support to mix real and symbolic. 2019-05-10 11:58:05 +02:00
CMakeLists.txt Add a fully generated documentation in the git repository. 2018-06-06 18:42:26 +02:00