coriolis/crlcore/etc/common
Jean-Paul Chaput 8035b31f27 First stage in analog capacitor integration
* Bug: In Technology::getPhysicalRule(), if the named layerdo not exists,
    throw an exception instead of silently putting a NULL pointer inside
    a rule.
* New: In Hurricane/Analog, new parameters classes for capacitor devices:
    - Analog::Matrix, a matrix of null or positives integers to encode
      capacitor matrix matching.
    - Analog::Capacities, a list of float values for all component of a
      multi-capacitor.
* New: In Hurricane::Script, add a "getFileName()" method to get the full
    path name of the Python module.
* Change: In Analog::LayoutGenerator, completly remove the logger utility
    as it is no longer used. Simply print error messages instead.
* Change: In Analog::MetaCapacitor, rename top & bottom plate 'T' & 'B'.
    Accessors renamed in "getTopPlate()" & "getBottomPlate()".
* New: In Analog::MultiCapacitor, complete rewrite. Makes use of the
    new parameters "capacities" and "matrix". Dynamically generates it's
    terminals as we do not know beforehand how many capacitors could be
    put in it.
* Bug: In isobar/PyHurricane.h, in Type object definition, do not prepend
    a "Py" to class name (so the keep the C++ name).
* Change: In CRL/etc/scn6m_deep_09/devices.py, add entry for the new
    capacitor generator.
* New: In oroshi/python/ParamsMatrix, add a "family" entry in the [0,0]
    element to distinguish between transistor, capacitor and resistor.
    (this is the matrix of values returned to the LayoutGenerator after
     device generation).
      Now have one "setGlobalParams()" function per family.
* New: In oroshi/python/Rules.py, added DTR rules needed by capacitors.
    Catch exceptions if something wrong append when we extract the rules
    from the technology.
* New: In Bora, the devices are no longer *only* transistors, so the
    possibles configurations are no longer defined only by a number of
    fingers. We must be able to support any kind of range of configuration.
      So the explicit range of number of fingers is replaced by a base
    class ParameterRange, and it's derived classes:
      - Bora::StepParameterRange, to encode the possible number of fingers
        of a transistor (the former only possibility).
      - Bora::MatrixParameterRange, to encode all the possible matching
        scheme for a capacitor. As there is no way to compress it, this
	is a vector of Matrix (from Analog).
* Change: In Bora::DSlicingNode::_place(), the ParameterRange has to be set
    on the right configuration (through the index) before being called.
      The generation parameters are taken from the active item in the
    ParameterRange.
* Change: In Bora::NodeSets::create(), iterate over the ParameterRange
    to build all the configuration. Adjustement to the routing gauge
    pitchs are moved into the DBoxSet CTOR to save a lot of code.
      Semantic change: the index in the NodeSets is now the index in
    the associated ParameterRange and no longer the number of fingers
    of a transistor.
      Check that the ParameterRange dynamic class is consitent with the
    device family.
* Change: In Bora::DBoxSet, same semantic change as for NodeSets, the
    number of finger become an index in ParameterRange.
      In DBoxSet::create(), now also perform the abutment box adjustement
    to the RoutingGauge, if possible.
* New: In Karakaze/python/AnalogDesign.py, add support for Capacitor
    devices.
2019-11-07 17:05:49 +01:00
..
__init__.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
analog.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
analog.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
colors.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
devices.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
devices.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
display.conf Correct CellWidget & CellPrinter to be really WYSIWYG. 2019-02-20 18:24:43 +01:00
display.py First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
etesian.conf Added core2chip support for Phenitec80. 2019-09-17 17:05:54 +02:00
etesian.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
hMetis.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
kite.conf Enable the display of GCells as a density map (and not boundaries). 2016-09-10 18:49:48 +02:00
kite.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
mauka.conf Buffer cell configuration in ClockTree. More config parameters in Chip. 2014-09-02 11:17:47 +02:00
misc.conf In CRL, update real conf. files. Smarter management of pin in LEF parser. 2018-01-06 16:18:33 +01:00
misc.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
nimbus.conf Bug in Python proxy deallocation. Update to latest Coloquinte. 2015-02-13 23:38:55 +01:00
patterns.conf Added METCAP layer, for MIM capacitors. 2016-03-06 12:40:23 +01:00
patterns.py First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
stratus1.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
stratus1.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
technology.conf Upgrade of Katana detailed router to support Arlet 6502. 2019-07-28 23:20:00 +02:00
technology.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00