147 lines
4.5 KiB
HTML
147 lines
4.5 KiB
HTML
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original version by: Nikos Drakos, CBLU, University of Leeds
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* revised and updated by: Marcus Hennecke, Ross Moore, Herb Swan
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* with significant contributions from:
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<H1><A NAME="SECTION000310000000000000000">
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DpgenRam</A>
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</H1>
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<UL>
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<LI><SPAN CLASS="textbf">Name</SPAN> : DpgenRam - RAM Macro-Generator
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</LI>
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<LI><SPAN CLASS="textbf">Synopsys</SPAN> :
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<PRE>
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Generate ( 'DpgenRam', modelname
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, param = { 'nbit' : n
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, 'nword' : regNumber
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, 'physical' : True
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}
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)
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</PRE>
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</LI>
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<LI><SPAN CLASS="textbf">Description</SPAN> : Generates a RAM of <code>regNumber</code> words of <code>n</code> bits named <code>modelname</code>.
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</LI>
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<LI><SPAN CLASS="textbf">Terminal Names</SPAN> :
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<UL>
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<LI><SPAN CLASS="textbf">ck</SPAN> : clock signal (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">w</SPAN> : write requested (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">selram</SPAN> : select the write bus (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">ad</SPAN> : the address (input, <code>Y</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">datain</SPAN> : write bus (input, <code>n</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">dataout</SPAN> : read bus (output, <code>n</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">vdd</SPAN> : power
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</LI>
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<LI><SPAN CLASS="textbf">vss</SPAN> : ground
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</LI>
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</UL>
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</LI>
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<LI><SPAN CLASS="textbf">Parameters</SPAN> : Parameters are given in the map <code>param</code>.
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<UL>
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<LI><SPAN CLASS="textbf">nbit</SPAN> (mandatory) : Defines the size of the generator
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</LI>
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<LI><SPAN CLASS="textbf">nword</SPAN> (mandatory) : Defines the size of the words
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</LI>
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<LI><SPAN CLASS="textbf">physical</SPAN> (optional, default value : False) : In order to generate a layout
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</LI>
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</UL>
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</LI>
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<LI><SPAN CLASS="textbf">Example</SPAN> :
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<PRE>
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from stratus import *
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class inst_ram ( Model ) :
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def Interface ( self ) :
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self.ck = SignalIn ( "ck", 1 )
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self.w = SignalIn ( "w", 1 )
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self.selram = SignalIn ( "selram", 1 )
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self.ad = SignalIn ( "ad", 5 )
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self.datain = SignalIn ( "datain", 32 )
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self.dataout = TriState ( "dataout", 32 )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Generate ( 'DpgenRam', 'ram_32_32'
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, param = { 'nbit' : 32
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, 'nword' : 32
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, 'physical' : True
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}
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)
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self.I = Inst ( 'ram_32_32', 'inst'
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, map = { 'ck' : self.ck
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, 'w' : self.w
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, 'selram' : self.selram
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, 'ad' : self.ad
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, 'datain' : self.datain
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, 'dataout' : self.dataout
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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def Layout ( self ) :
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Place ( self.I, NOSYM, Ref(0, 0) )
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</PRE>
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</LI>
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</UL>
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<BR> <HR>
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<ADDRESS>
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Sophie B<small>ELLOEIL</small><br>20051116.1
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</ADDRESS>
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