126 lines
7.3 KiB
C++
126 lines
7.3 KiB
C++
#include <string>
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using namespace std;
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#include "vlsisapd/openChams/Circuit.h"
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#include "vlsisapd/openChams/Netlist.h"
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#include "vlsisapd/openChams/Instance.h"
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#include "vlsisapd/openChams/Device.h"
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#include "vlsisapd/openChams/Transistor.h"
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#include "vlsisapd/openChams/Net.h"
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#include "vlsisapd/openChams/Schematic.h"
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#include "vlsisapd/openChams/Sizing.h"
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#include "vlsisapd/openChams/Operator.h"
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#include "vlsisapd/openChams/Layout.h"
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#include "vlsisapd/openChams/Node.h"
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#include "vlsisapd/openChams/Port.h"
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#include "vlsisapd/openChams/Wire.h"
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int main(int argc, char * argv[]) {
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OpenChams::Circuit* circuit = new OpenChams::Circuit(OpenChams::Name("design"), OpenChams::Name("myTech"));
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// value parameters
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circuit->addParameter(OpenChams::Name("temp"), "27.0" );
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circuit->addParameter(OpenChams::Name("Vdd") , "1.2" );
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circuit->addParameter(OpenChams::Name("Vss") , "0.0" );
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circuit->addParameter(OpenChams::Name("L") , "0.1e-6");
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circuit->addParameter(OpenChams::Name("Ids") , "30e-6" );
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circuit->addParameter(OpenChams::Name("Veg") , "0.12" );
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// equation parameters
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circuit->addParameter(OpenChams::Name("complex"), "myEq");
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// netlist
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OpenChams::Netlist* netlist = circuit->createNetlist();
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// instances
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// nmos1
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OpenChams::Device* inst_nmos1 = netlist->addDevice(OpenChams::Name("nmos1"), OpenChams::Name("Transistor"), 1, OpenChams::Name("NMOS"), true);
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inst_nmos1->addConnector(OpenChams::Name("G"));
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inst_nmos1->addConnector(OpenChams::Name("S"));
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inst_nmos1->addConnector(OpenChams::Name("D"));
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OpenChams::Transistor* tr_nmos1 = inst_nmos1->addTransistor(OpenChams::Name("m1"));
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tr_nmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_nmos1
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tr_nmos1->setSource(OpenChams::Name("S"));
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tr_nmos1->setDrain (OpenChams::Name("D"));
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tr_nmos1->setBulk (OpenChams::Name("S"));
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// pmos1
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OpenChams::Device* inst_pmos1 = netlist->addDevice(OpenChams::Name("pmos1"), OpenChams::Name("Transistor"), 2, OpenChams::Name("PMOS"), true);
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inst_pmos1->addConnector(OpenChams::Name("G"));
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inst_pmos1->addConnector(OpenChams::Name("S"));
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inst_pmos1->addConnector(OpenChams::Name("D"));
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OpenChams::Transistor* tr_pmos1 = inst_pmos1->addTransistor(OpenChams::Name("m1"));
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tr_pmos1->setGate (OpenChams::Name("G")); // the name of the connector of inst_pmos1
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tr_pmos1->setSource(OpenChams::Name("S"));
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tr_pmos1->setDrain (OpenChams::Name("D"));
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tr_pmos1->setBulk (OpenChams::Name("S"));
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// nets
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OpenChams::Net* _vdd = netlist->addNet(OpenChams::Name("vdd"), OpenChams::Name("power") , true);
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OpenChams::Net* _vss = netlist->addNet(OpenChams::Name("vss"), OpenChams::Name("ground") , true);
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OpenChams::Net* _in = netlist->addNet(OpenChams::Name("in" ), OpenChams::Name("logical"), true);
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OpenChams::Net* _out = netlist->addNet(OpenChams::Name("out"), OpenChams::Name("logical"), true);
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_vdd->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("S"));
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_vss->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("S"));
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_in->connectTo (OpenChams::Name("nmos1"), OpenChams::Name("G"));
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_in->connectTo (OpenChams::Name("pmos1"), OpenChams::Name("G"));
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_out->connectTo(OpenChams::Name("nmos1"), OpenChams::Name("D"));
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_out->connectTo(OpenChams::Name("pmos1"), OpenChams::Name("D"));
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// schematic
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OpenChams::Schematic* schematic = circuit->createSchematic();
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schematic->addInstance(OpenChams::Name("nmos1"), 2490, 2600, OpenChams::Name("ID"));
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schematic->addInstance(OpenChams::Name("pmos1"), 2490, 2300, OpenChams::Name("ID"));
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_vdd->addPort(OpenChams::Name("inV"), 0, 2490, 2100, OpenChams::Name("ID"));
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OpenChams::Wire* wVdd = _vdd->addWire();
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wVdd->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("S"));
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wVdd->setEndPoint (0);
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_vss->addPort(OpenChams::Name("inV"), 0, 2490, 2800, OpenChams::Name("MY"));
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OpenChams::Wire* wVss = _vss->addWire();
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wVss->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("S"));
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wVss->setEndPoint (0);
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_in->addPort(OpenChams::Name("inH"), 0, 2190, 2500, OpenChams::Name("ID"));
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OpenChams::Wire* wIn = _in->addWire();
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wIn->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("G"));
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wIn->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("G"));
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OpenChams::Wire* wIn1 = _in->addWire();
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wIn1->setStartPoint(0);
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wIn1->setEndPoint (OpenChams::Name("pmos1"), OpenChams::Name("G"));
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_out->addPort(OpenChams::Name("outH"), 0, 2600, 2500, OpenChams::Name("ID"));
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OpenChams::Wire* wOut = _out->addWire();
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wOut->setStartPoint(OpenChams::Name("pmos1"), OpenChams::Name("D"));
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wOut->setEndPoint (OpenChams::Name("nmos1"), OpenChams::Name("D"));
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OpenChams::Wire* wOut1 = _out->addWire();
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wOut1->setStartPoint(OpenChams::Name("nmos1"), OpenChams::Name("D"));
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wOut1->setEndPoint (0);
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// sizing
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OpenChams::Sizing* sizing = circuit->createSizing();
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OpenChams::Operator* op_pmos1 = sizing->addOperator(OpenChams::Name("pmos1"), OpenChams::Name("OPVG(Veg)"), OpenChams::Name("BSIM3V3"));
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op_pmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
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op_pmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids") );
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op_pmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L") );
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op_pmos1->addConstraint(OpenChams::Name("Veg") , OpenChams::Name("design"), OpenChams::Name("Veg") );
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op_pmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("design"), OpenChams::Name("Vdd") , 0.5);
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op_pmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd") );
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OpenChams::Operator* op_nmos1 = sizing->addOperator(OpenChams::Name("nmos1"), OpenChams::Name("OPW(Vg,Vs)"), OpenChams::Name("BSIM3V3"));
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op_nmos1->addConstraint(OpenChams::Name("Temp"), OpenChams::Name("design"), OpenChams::Name("temp"));
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op_nmos1->addConstraint(OpenChams::Name("Ids") , OpenChams::Name("design"), OpenChams::Name("Ids" ));
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op_nmos1->addConstraint(OpenChams::Name("L") , OpenChams::Name("design"), OpenChams::Name("L" ));
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op_nmos1->addConstraint(OpenChams::Name("Vs") , OpenChams::Name("design"), OpenChams::Name("Vdd" ));
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op_nmos1->addConstraint(OpenChams::Name("Vg") , OpenChams::Name("pmos1") , OpenChams::Name("Vg" ));
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op_nmos1->addConstraint(OpenChams::Name("Vd") , OpenChams::Name("pmos1") , OpenChams::Name("Vd" ));
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op_nmos1->addConstraint(OpenChams::Name("another"), OpenChams::Name("myEq"), -2.5 );
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// layout
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OpenChams::Layout* layout = circuit->createLayout();
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layout->addInstance(OpenChams::Name("pmos1"), OpenChams::Name("Common transistor"));
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layout->addInstance(OpenChams::Name("nmos1"), OpenChams::Name("Rotate transistor"));
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// create hbtree
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OpenChams::Group* g1 = new OpenChams::Group("g1"); // default position is NONE and default parent is NULL
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g1->setAlign(OpenChams::Group::VERTICAL);
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OpenChams::Bloc* b1 = new OpenChams::Bloc("nmos1", OpenChams::Node::NONE, g1);
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g1->setRootNode(b1); // b1 is root node of group g1
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OpenChams::Bloc* b2 = new OpenChams::Bloc("pmos1", OpenChams::Node::TOP, b1);
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b1->setTop(b2); // b2 is on top of b1
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layout->setHBTreeRoot(g1); // g1 is the root of the tree
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circuit->writeToFile("./myInverter.xml");
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return 0;
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}
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