fe32916d14
It is now possible to automatically nest a core block inside a harness
frame, like we do for an ordinary chip whith I/O pads. The DEF harness
file "user_project_wrapper.def" must be made available though the block
configuration variable:
conf.cfg.harness.path = './user_project_wrapper.def'
A first small example is given in:
alliance-check-toolkit/benchs/counter/sky130_c4m
The harness layout is stripped from it's native power grid (but keep
the power ring). I/O pad information in block/configuration is
slightly "bent* to manage pins instead of complete I/O pads.
* Bug: In cumulus/plugins.block.Block.setupAb(), the routingBb was not
set up when working in chip mode. Now set (to the corona AB).
* Change: In cumulus/plugins.chip.__init__, move there the CoreWire
class (from chip/pads.py) so it can be shared with the harness
version of pads.py.
* Change: In cumulus/plugins.chip.powerplane, compute the intersection
between the vertical supply stripes and the deep horizontal power
lines in a smarter fashion, so two (or more) vertically contiguous
BigVias are merged into one (two BigVia side by side where causing
mimimal spacing distance violation on the cut in Sky130).
|
||
|---|---|---|
| .. | ||
| src | ||
| CMakeLists.txt | ||