coriolis/crlcore/etc/common
Jean-Paul Chaput 3dbaea6aca Bug fix, restore the FreePDK 45 (real) support.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
    newly read MACRO (that is Cell) and sets the Logical, Physical,
    InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
    cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
    layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
    new Python "importable" format.
      Note: in kite.py, all the gauges (Routing & Cells) must be named
    "LEF.CoreSite" to please my LEF parser, so it can match the gauge
    name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
    from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
    from the layers in the RoutingGauge and their associated blockages
    instead of sweeping through all the basic layers.
      Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
2020-04-27 10:34:19 +02:00
..
__init__.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
analog.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
analog.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
colors.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
devices.conf Anlog integration part I. Atomic devices support (transistors). 2018-10-01 16:52:17 +02:00
devices.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
display.conf Correct CellWidget & CellPrinter to be really WYSIWYG. 2019-02-20 18:24:43 +01:00
display.py More configuration parameters for P&R Conductor, for experimenting. 2019-12-15 19:28:54 +01:00
etesian.conf Added core2chip support for Phenitec80. 2019-09-17 17:05:54 +02:00
etesian.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
hMetis.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
kite.conf Enable the display of GCells as a density map (and not boundaries). 2016-09-10 18:49:48 +02:00
kite.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
mauka.conf Buffer cell configuration in ClockTree. More config parameters in Chip. 2014-09-02 11:17:47 +02:00
misc.conf In CRL, update real conf. files. Smarter management of pin in LEF parser. 2018-01-06 16:18:33 +01:00
misc.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
nimbus.conf Bug in Python proxy deallocation. Update to latest Coloquinte. 2015-02-13 23:38:55 +01:00
patterns.conf Added METCAP layer, for MIM capacitors. 2016-03-06 12:40:23 +01:00
patterns.py First stage in analog capacitor integration 2019-11-07 17:05:49 +01:00
stratus1.conf More configuration sharing. 2014-05-27 15:40:42 +02:00
stratus1.py Migrating the initialisation system to be completely Python-like. 2019-10-28 18:09:14 +01:00
technology.conf Upgrade of Katana detailed router to support Arlet 6502. 2019-07-28 23:20:00 +02:00
technology.py Bug fix, restore the FreePDK 45 (real) support. 2020-04-27 10:34:19 +02:00