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coriolis
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coriolis/crlcore
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Jean-Paul Chaput 84d25da1b8 More thorough verification of outputs of tie low/tie high in Blif parser. 
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
    of the tie low & tie high cells check if the net name is not a
    power or ground. A bad input was choosen with FlexLib as the
    vdd/vss nets where not typed as POWER/GROUND.
 		2020-12-03 16:34:22 +01:00
..
cmake_modules Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
doc Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
etc Tag contacts layers as symbolic in CRL/etc/common/technology.py 2020-12-02 20:04:27 +01:00
python Add area parameter to createBL() helper function. 2020-11-26 17:25:52 +01:00
src More thorough verification of outputs of tie low/tie high in Blif parser. 2020-12-03 16:34:22 +01:00
CMakeLists.txt Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00