coriolis/crlcore/src
Jean-Paul Chaput 51a3236962 Add management of fixed wires to Kite (for chip ClockTree)
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
    variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
    is copied up as blockage. Uses blockage layer instead of true layer
    (it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
    nets with only default wiring (default size wire & contacts).
    Non-default routing is flagged as fixed (with the NetRoutingState
    property).
2014-08-15 19:26:49 +02:00
..
ccore In ACSII/GDS driver, process the complete hierarchy. 2014-08-15 11:48:41 +02:00
crlcore First basic version of ClockTree & Chip plugins. 2014-08-15 19:05:27 +02:00
cyclop Add management of fixed wires to Kite (for chip ClockTree) 2014-08-15 19:26:49 +02:00
fonts * ./hurricane/src/hviewer, 2010-03-09 15:20:13 +00:00
pyCRL Complete replacement of the Chip placement Python scripts. 2014-07-21 13:18:34 +02:00
x2y Update to Qt 5, requires cmake 2.8.9. New placer: Etesian. 2014-03-22 11:50:36 +01:00
CMakeLists.txt * All Tools: 2012-12-03 08:27:41 +00:00