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coriolis/crlcore/src
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Jean-Paul Chaput 84d25da1b8 More thorough verification of outputs of tie low/tie high in Blif parser. 
* Change: In CRL::Model::staticInit(), when trying to guess the ouput
    of the tie low & tie high cells check if the net name is not a
    power or ground. A bad input was choosen with FlexLib as the
    vdd/vss nets where not typed as POWER/GROUND.
 		2020-12-03 16:34:22 +01:00
..
LibraryManager Bug fixes in Blif parser (no VHDL enforcement) & GDS driver. 2019-03-07 20:14:08 +01:00
ccore More thorough verification of outputs of tie low/tie high in Blif parser. 2020-12-03 16:34:22 +01:00
cyclop In Cyclop CMakeLists, cleanup the switch Qt4/Qt5. 2019-11-10 12:28:50 +01:00
fonts * ./hurricane/src/hviewer, 2010-03-09 15:20:13 +00:00
pyCRL DRC correct on Arlet6505 / TSMC C180. 2020-11-23 23:07:15 +01:00
x2y Diplay function, file & line number in the backtrace (like gdb). 2016-08-06 18:15:06 +02:00
CMakeLists.txt New Library Manager Widget. Access with Tools menu or CTRL+M. 2015-05-09 17:03:17 +02:00