After a Cell has been created in memory (by parsers or Python scripts)
we can annotate it with the Spice parser so it will know the right
order with which to create the subcircuit call ('x').
* New: In CRL::Spice::load(), add support to read the ".subckt" card
and guess the right ordering for generating the 'x' (subcircuit
card call).
* Bug: In Spice::SpiceBit & Spice::BitExtension, when a Net bit property
is removed, if it's the currently cached property in BitExtension
it may lead to a crash. So when a property is destroyed, we must
also clear the cache (see remove(), clearCache() & onReleasedby()).
I'm wary that this could also happen on other kind of cached
extensions...
* New: In CRL::NamingScheme, new method vhdlToVlog() to translate back
VHDL net name into Verilog. Currently only changes "()" into "[]".
Used to generate the commented SPICE interface for Alliance compliance.
* Change: In Spice::Entity, previously all the ordering where removed
between each run of the SPICE parser, but the orders read from
SPICE file (mostly standard cells) must be kept. So add a flag
ReferenceCell to prevent the removal by ::destroyAll().
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