74 lines
3.5 KiB
TeX
74 lines
3.5 KiB
TeX
\subsection{Synopsys}
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\begin{verbatim}
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netInput = SignalIn ( name, arity )
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\end{verbatim}
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\subsection{Description}
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Instanciation of net. Differents kind of nets are listed below :
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\begin{itemize}
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\item \verb-SignalIn- : Creation of an input port
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\item \verb-SignalOut- : Creation of an output port
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\item \verb-SignalInOut- : Creation of an inout port
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\item \verb-SignalUnknown- : Creation of an input/output port which direction is not defined
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\item \verb-TriState- : Creation of a tristate port
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\item \verb-CkIn- : Creation of a clock port
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\item \verb-VddIn- : Creation of the vdd alimentation
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\item \verb-VssIn- : Creation of the vss alimentation
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\item \verb-Signal- : Creation of an internal net
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\end{itemize}
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\subsection{Parameters}
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\begin{itemize}
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\item \verb-name- : Name of the net (mandatory argument)
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\item \verb-arity- : Arity of the net (mandatory argument)
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\item \verb-indice- : For buses only : the LSB bit (optional argument : set to 0 by default)\\
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\end{itemize}
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\indent Only \verb-CkIn, -\verb-VddIn- and \verb-VssIn- do not have the same parameters : there is only the \verb-name- parameter (they are 1 bit nets).
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\subsection{Attributes}
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\begin{itemize}
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\item \verb-_name- : Name of the net
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\item \verb-_arity- : Arity of the net (by default set to 0)
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\item \verb-_ind- : LSB of the net
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\item \verb-_ext- : Tells if the net is external or not (True/False)
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\item \verb-_direct- : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN")
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\item \verb-_h_type- : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK")
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\item \verb-_type- : The arithmetic type of the net ( "nr" )
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\item \verb-_st_cell- : The stratus cell which the net is instanciated in
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\item \verb-_real_net- : If the net is a part of a net (Sig) it is the real net corresponding
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\item \verb-_alias- : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net
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\item \verb-_to_merge- : [] by default. The same as \_alias
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\item \verb-_to_cat- : [] by default. The same as \_alias\\
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\end{itemize}
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\indent And, in connection with Hurricane :
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\begin{itemize}
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\item \verb-_hur_net- : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : \verb-net._hur_net[0]- ).
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\end{itemize}
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\subsection{Methods}
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\begin{itemize}
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\item \verb-Buffer- : Instanciation of a Buffer
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\item \verb-Shift- : Instanciation of a shifter
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\item \verb-Mux- : Instanciation of a multiplexor
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\item \verb-Reg- : Instanciation of a register
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\item \verb-Eq/Ne- : Instanciation of comparison generator
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\item \verb-Extend- : A net is extended
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\item \verb-Alias- : A net is an alias of another net
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\item \verb-Delete- : Deletion of the Hurricane nets\\
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\end{itemize}
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\indent And the overloards :
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\begin{itemize}
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\item \_\_init\_\_ : Initialisation of nets
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\item \_\_le\_\_ : initialisation of a net thanks to <= notation
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\item \_\_getitem\_\_, \_\_geslice\_\_ : Creation of "Sig" nets : which are part of nets (use of \verb-[]- and \verb-[:]-)
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\item \_\_and\_\_, \_\_or\_\_, \_\_xor\_\_, \_\_invert\_\_ : boolean operation with \&, |, \^ , ~
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\item \_\_add\_\_, \_\_mul\_\_, \_\_div\_\_ : arithmetic operators with +, * and /
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\end{itemize}
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