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<h1 class="header-title text-uppercase">RDS / Symbolic to Real Conversion</h1>
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<div class="header-underline"></div>
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<!-- -*- mode: rst; explicit-buffer-name: "RDS_HTML.rst<pelican>" -*- -->
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<!-- -*- Mode: rst; explicit-buffer-name: "definition.rst<documentation/etc>" -*- -->
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<!-- HTML/LaTeX backends mixed macros. -->
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<!-- Acronyms & names. -->
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<!-- Standard CAO/VLSI Concepts. -->
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<!-- Alliance & MBK Concepts -->
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<div class="section" id="printable-version-of-this-document">
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<h2><a class="toc-backref" href="#id2">Printable version of this Document</a></h2>
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<p><a class="reference external" href="../pdfs/RDS.pdf">RDS.pdf</a></p>
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<div class="contents topic" id="contents">
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<p class="topic-title">Contents</p>
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<ul class="simple">
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<li><a class="reference internal" href="#printable-version-of-this-document" id="id2">Printable version of this Document</a></li>
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<li><a class="reference internal" href="#symbolic-layout" id="id3">Symbolic Layout</a><ul>
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<li><a class="reference internal" href="#symbolic-components" id="id4">Symbolic Components</a></li>
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<li><a class="reference internal" href="#symbolic-segments" id="id5">Symbolic Segments</a></li>
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</ul>
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</li>
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<li><a class="reference internal" href="#the-rds-file" id="id6">The RDS File</a><ul>
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<li><a class="reference internal" href="#physical-grid-lambda-value" id="id7">Physical Grid & Lambda Value</a></li>
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<li><a class="reference internal" href="#the-mbk-to-rds-segment-table" id="id8">The <tt class="docutils literal">MBK_TO_RDS_SEGMENT</tt> table</a></li>
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<li><a class="reference internal" href="#the-mbk-to-rds-via-table" id="id9">The <tt class="docutils literal">MBK_TO_RDS_VIA</tt> table</a></li>
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<li><a class="reference internal" href="#the-mbk-to-rds-bigvia-hole-table" id="id10">The <tt class="docutils literal">MBK_TO_RDS_BIGVIA_HOLE</tt> table</a></li>
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<li><a class="reference internal" href="#the-mbk-to-rds-bigvia-metal-table" id="id11">The <tt class="docutils literal">MBK_TO_RDS_BIGVIA_METAL</tt> table</a></li>
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<li><a class="reference internal" href="#the-mbk-wiresetting-table" id="id12">The <tt class="docutils literal">MBK_WIRESETTING</tt> table</a></li>
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</ul>
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</li>
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</ul>
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</div>
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<p><strong>Disclaimer:</strong> This document is still far from complete.</p>
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<!-- -*- Mode: rst -*- -->
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<!-- Tools -->
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<!-- RDS file syntax. -->
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<p></p>
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</div>
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<div class="section" id="symbolic-layout">
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<h2><a class="toc-backref" href="#id3">Symbolic Layout</a></h2>
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<div class="section" id="symbolic-components">
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<h3><a class="toc-backref" href="#id4">Symbolic Components</a></h3>
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<p>A symbolic layout is, in practice, made of only of three objects:</p>
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<table class="table">
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<colgroup>
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<col width="30%" />
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<col width="13%" />
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<col width="57%" />
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</colgroup>
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<thead valign="bottom">
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<tr><th class="head">Object</th>
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<th class="head"><span class="sc">mbk</span></th>
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<th class="head">Explanation</th>
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</tr>
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</thead>
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<tbody valign="top">
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<tr><td>Segments</td>
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<td><tt class="docutils literal">phseg</tt></td>
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<td>Oriented segments with a width and an orientation.</td>
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</tr>
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<tr><td>VIAs & contacts</td>
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<td><tt class="docutils literal">phvia</tt></td>
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<td>Boils down to just a point.</td>
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</tr>
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<tr><td>Big VIAs & Big Contacts</td>
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<td><tt class="docutils literal">phvia</tt></td>
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<td>Point with a width and a height
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That is a rectangle of width by height centered
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on the VIA coordinates.</td>
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</tr>
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</tbody>
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</table>
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<p>Each of thoses objects is associated to a <em>symbolic layer</em> which will
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control how the object is translated in many <em>real rectangles</em>.</p>
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<table class="table">
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<colgroup>
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<col width="11%" />
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<col width="19%" />
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<col width="16%" />
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<col width="54%" />
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</colgroup>
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<thead valign="bottom">
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<tr><th class="head"><span class="sc">mbk</span></th>
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<th class="head">Layer Name</th>
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<th class="head">Usable By</th>
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<th class="head">Usage</th>
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</tr>
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</thead>
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<tbody valign="top">
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<tr><td rowspan="12"><tt class="docutils literal">phseg</tt></td>
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<td><span class="sc">nwell</span></td>
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<td>Segment</td>
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<td>N Well</td>
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</tr>
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<tr><td><tt class="docutils literal">PWELL</tt></td>
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<td>Segment</td>
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<td>P Well</td>
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</tr>
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<tr><td><tt class="docutils literal">NDIF</tt></td>
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<td>Segment</td>
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<td>N Diffusion</td>
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</tr>
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<tr><td><tt class="docutils literal">PDIF</tt></td>
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<td>Segment</td>
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<td>P Diffusion</td>
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</tr>
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<tr><td><tt class="docutils literal">NTIE</tt></td>
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<td>Segment</td>
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<td>N Tie</td>
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</tr>
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<tr><td><tt class="docutils literal">PTIE</tt></td>
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<td>Segment</td>
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<td>P Tie</td>
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</tr>
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<tr><td><tt class="docutils literal">NTRANS</tt></td>
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<td>Segment</td>
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<td>N transistor, in <span class="sc">Alliance</span>, a transistor
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is represented as a segment (it's grid).</td>
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</tr>
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<tr><td><tt class="docutils literal">PTRANS</tt></td>
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<td>Segment</td>
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<td>P transistor</td>
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</tr>
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<tr><td><tt class="docutils literal">POLY</tt></td>
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<td>Segment</td>
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<td>Polysilicium</td>
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</tr>
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<tr><td><tt class="docutils literal">ALUx</tt></td>
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<td>Segment</td>
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<td>Metal level <em>x</em></td>
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</tr>
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<tr><td><tt class="docutils literal">CALUx</tt></td>
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<td>Segment</td>
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<td>Metal level <em>x</em>, that can be used by the
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upper hierarchical level as a connector.
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From the layout point of view it is the
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same as <tt class="docutils literal">ALUx</tt>.</td>
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</tr>
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<tr><td><tt class="docutils literal">TALUx</tt></td>
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<td>Segment</td>
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<td>Blockage for metal level <em>x</em>. Will
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diseappear in the real layout as it is an
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information for the P&R tools only.</td>
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</tr>
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<tr><td rowspan="9"><tt class="docutils literal">phvia</tt></td>
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<td><tt class="docutils literal">CONT_BODY_N</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact to N Well</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_BODY_P</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact to P Well</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_DIF_N</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact to N Diffusion</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_DIF_P</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact to P Diffusion</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_POLY</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact to polysilicium</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_VIA</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact between metal1 and metal2</td>
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</tr>
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<tr><td><tt class="docutils literal">CONT_VIAx</tt></td>
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<td>VIA, BIGVIA</td>
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<td>Contact between metal <em>x</em> and metal <em>x+1</em>.
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The index is the the one of the bottom
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metal of the VIA.</td>
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</tr>
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<tr><td><tt class="docutils literal">C_X_N</tt></td>
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<td>VIA</td>
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<td>N transistor corner, to build transistor
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bend. Not used anymore in recent technos</td>
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</tr>
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<tr><td><tt class="docutils literal">C_X_P</tt></td>
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<td>VIA</td>
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<td>P transistor corner, to build transistor
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bend. Not used anymore in recent technos</td>
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</tr>
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</tbody>
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</table>
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<div class="admonition note">
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<p class="first admonition-title">Note</p>
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<p class="last">Not all association of object and symbolic layers are meaningful.
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For instance you cannot associate a contact to a <tt class="docutils literal">NTRANS</tt> layer.</p>
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</div>
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<div class="admonition note">
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<p class="first admonition-title">Note</p>
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<p class="last">The symbolic layer associated with blockages is prefixed by a <tt class="docutils literal">T</tt>,
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for <em>transparency</em>, which may seems silly. It is for historical reasons,
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it started as a true transparency, but at some point we had to invert
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the meaning (blockage) with the rise of over-the-cell routing, but the
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name stuck...</p>
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</div>
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</div>
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<div class="section" id="symbolic-segments">
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<h3><a class="toc-backref" href="#id5">Symbolic Segments</a></h3>
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<p>In <span class="sc">Alliance</span>, segments are oriented (up, down, left, right). This disambiguate
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the left or right side when using the <tt class="docutils literal">LCW</tt> and <tt class="docutils literal">RCW</tt> rules in the <span class="sc">rds</span> file.
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It allows to generate, if needed, asymetric object in the real layout file.</p>
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<p> <img alt="Symbolic Segment Orientations" class="align-middle" src="../pages/images/SegmentOrientation.png" style="width: 50%;" /> </p>
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<p></p>
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</div>
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</div>
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<div class="section" id="the-rds-file">
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<h2><a class="toc-backref" href="#id6">The RDS File</a></h2>
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<p>The RDS file control how a symbolic layout is transformed into it's real
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conterpart.</p>
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<div class="admonition note">
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<p class="first admonition-title">Note</p>
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<p class="last"><strong>Unit used inside the RDS file:</strong> all units are expressed in micrometers.</p>
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</div>
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<p>Alliance tools relying on the RDS file, and what layers are active for them:</p>
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<table class="table">
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|
<colgroup>
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<col width="47%" />
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|
<col width="16%" />
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<col width="37%" />
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</colgroup>
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<thead valign="bottom">
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<tr><th class="head">Tool</th>
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<th class="head">Name</th>
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<th class="head">RDS Flags</th>
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</tr>
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</thead>
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<tbody valign="top">
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<tr><td>Layout editor</td>
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<td><tt class="docutils literal">graal</tt></td>
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<td><tt class="docutils literal">ALL</tt></td>
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</tr>
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<tr><td>Design Rule Checker</td>
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<td><tt class="docutils literal">druc</tt></td>
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<td><tt class="docutils literal">ALL</tt>, <tt class="docutils literal">DRC</tt></td>
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</tr>
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<tr><td>Electrical extractor</td>
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<td><tt class="docutils literal">cougar</tt></td>
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<td><tt class="docutils literal">ALL</tt>, <tt class="docutils literal">EXT</tt></td>
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</tr>
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<tr><td>The symbolic to real layout translator</td>
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<td><span class="cb">s2r</span></td>
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<td><tt class="docutils literal">ALL</tt></td>
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</tr>
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</tbody>
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</table>
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|
<div class="section" id="physical-grid-lambda-value">
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<h3><a class="toc-backref" href="#id7">Physical Grid & Lambda Value</a></h3>
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<p>RDS file:</p>
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<pre class="literal-block">
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DEFINE PHYSICAL_GRID 0.005
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DEFINE LAMBDA 0.09
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</pre>
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<p>Tells that the physical grid (founder grid) step is 0.005µm and the lambda has
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a value of 0.09µm. That is, one lambda is 18 grid steps.</p>
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<p>We can distinguish two kind of <span class="sc">rds</span> files:</p>
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<ul class="simple">
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<li>The <em>1µm</em> kind, odd segment widths and coordinates are allowed, but the <tt class="docutils literal">LAMBDA</tt>
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value <strong>must</strong> represent an <em>even</em> number of foundry grid step.</li>
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<li>The <em>2µm</em> kind, segments widths and coordinates must all be even. And in that case
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the <tt class="docutils literal">LAMBDA</tt> value can be any multiple of the foundry grid.</li>
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</ul>
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</div>
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<div class="section" id="the-mbk-to-rds-segment-table">
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<h3><a class="toc-backref" href="#id8">The <tt class="docutils literal">MBK_TO_RDS_SEGMENT</tt> table</a></h3>
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<p>The <tt class="docutils literal">MBK_TO_RDS_SEGMENT</tt> table control the way segments are translated into
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real rectangles. Be aware that we are translating <em>segments</em> and not <em>rectangles</em>.
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Segments are defined by their axis (source & target points) and their width.
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The geometrical transformations are described according to that model.
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Obviously, they are either horizontal or vertical.</p>
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<p>The translation method of a symbolic segment is as follow:</p>
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<ol class="arabic">
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<li><p class="first">The segment is translated into one or more physical rectangles.
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The generated rectangles depends on the tool which is actually
|
|
using <span class="sc">rds</span> and the flag for the considered real layer.
|
|
For instance, real layers flagged with <tt class="docutils literal">DRC</tt> will be generated
|
|
for <span class="cb">s2r</span> (for the <tt class="docutils literal">cif</tt> or <tt class="docutils literal">gds</tt>) and <tt class="docutils literal">druc</tt>, but will not
|
|
be shown under <tt class="docutils literal">graal</tt>.</p>
|
|
</li>
|
|
<li><p class="first">Translation into one real layer. <em>First</em> the source & target coordinates and width
|
|
of the symbolic segment are multiplied by the <tt class="docutils literal">LAMBDA</tt> value to obtain a real
|
|
segment. <em>Then</em> one of the <tt class="docutils literal">VW</tt>, <tt class="docutils literal">LCW</tt> or <tt class="docutils literal">RCW</tt> transformation is applied to
|
|
that segment to get the final real rectangle.</p>
|
|
<ul>
|
|
<li><p class="first"><tt class="docutils literal">VW</tt> for Variable Width, expand the real layer staying centered from the
|
|
original one. In those rules, the third number is not used, it is only here
|
|
to make the life easier for the parser...</p>
|
|
<p> <img alt="RDS Variable Width Rule" class="align-middle" src="../pages/images/RDS_VW.png" style="width: 60%;" /> </p>
|
|
</li>
|
|
<li><p class="first"><tt class="docutils literal">LCW</tt> or <tt class="docutils literal">RCW</tt> for Left/Right Constant Width, create an off-center rectangle
|
|
of fixed width relatively to the real segment. Note that the <tt class="docutils literal">SP</tt> number
|
|
is the distance <em>between the edge</em> of the real segment and the edge of the
|
|
generated real rectangle (<em>not</em> from the axis). It is often zero.</p>
|
|
<p> <img alt="RDS Left Constant Width Rule" class="align-middle" src="../pages/images/RDS_LCW.png" style="width: 40%;" /> </p>
|
|
</li>
|
|
</ul>
|
|
</li>
|
|
</ol>
|
|
<p></p>
|
|
<p>Examples:</p>
|
|
<pre class="literal-block">
|
|
TABLE MBK_TO_RDS_SEGMENT
|
|
|
|
# (Case 1)
|
|
ALU1 RDS_ALU1 VW 0.18 0.09 0.0 ALL
|
|
|
|
# (Case 2)
|
|
NDIF RDS_NDIF VW 0.18 0.0 0.0 ALL \
|
|
RDS_ACTIV VW 0.18 0.0 0.0 DRC \
|
|
RDS_NIMP VW 0.36 0.36 0.0 DRC
|
|
|
|
# (Case 3)
|
|
NTRANS RDS_POLY VW 0.27 0.00 0.0 ALL \
|
|
RDS_GATE VW 0.27 0.00 0.0 DRC \
|
|
RDS_NDIF LCW 0.0 0.27 0.0 EXT \
|
|
RDS_NDIF RCW 0.0 0.27 0.0 EXT \
|
|
RDS_NDIF VW 0.0 0.72 0.0 DRC \
|
|
RDS_ACTIV VW 0.0 0.72 0.0 ALL \
|
|
RDS_NIMP VW 0.18 1.26 0.0 DRC
|
|
|
|
END
|
|
</pre>
|
|
<p><span class="fboxtt">Case 1</span> the <tt class="docutils literal">ALU1</tt> is translated in exacltly one real rectangle of
|
|
<tt class="docutils literal">RDS_ALU1</tt>, both ends are extended by 0.18µm and it's width is increased
|
|
by 0.09µm.</p>
|
|
<p><span class="fboxtt">Case 2</span> the <tt class="docutils literal">NDIF</tt> will be translated into only one segment
|
|
under <tt class="docutils literal">graal</tt>, for symbolic visualization. And into three real rectangles
|
|
for <span class="cb">s2r</span> and <tt class="docutils literal">druc</tt>.</p>
|
|
<p><span class="fboxtt">Case 3</span> the <tt class="docutils literal">NTRANS</tt>, associated to a transistor is a little bit
|
|
more complex, the generated shapes are different for the extractor <tt class="docutils literal">cougar</tt>
|
|
in one hand, and for both <tt class="docutils literal">druc</tt> & <span class="cb">s2r</span> in the other hand.</p>
|
|
<ul>
|
|
<li><p class="first">For the extractor (<tt class="docutils literal">EXT</tt> & <tt class="docutils literal">ALL</tt> flags) there will be four rectangles
|
|
generateds:</p>
|
|
<ol class="arabic simple">
|
|
<li>The gate (<tt class="docutils literal">RDS_GATE</tt>)</li>
|
|
<li>The left diffusion of the transistor (source or drain) (<tt class="docutils literal">RDS_NDIF</tt>).</li>
|
|
<li>The right diffusion of the transistor (drain or source) (<tt class="docutils literal">RDS_NDIF</tt>).</li>
|
|
<li>The active area (<tt class="docutils literal">RDS_ACTIV</tt>).</li>
|
|
</ol>
|
|
<p>As the extractor must kept separate the source and the drain of the transistor,
|
|
they are generated as two offset rectangles, using the <tt class="docutils literal">LCW</tt> and <tt class="docutils literal">RCW</tt> directives.</p>
|
|
</li>
|
|
<li><p class="first">For <span class="cb">s2r</span> and <tt class="docutils literal">druc</tt> (<tt class="docutils literal">DRC</tt> and <tt class="docutils literal">ALL</tt>), five rectangles are generateds:</p>
|
|
<ol class="arabic simple">
|
|
<li>The poly (<tt class="docutils literal">RDS_POLY</tt>).</li>
|
|
<li>The gate (<tt class="docutils literal">RDS_GATE</tt>).</li>
|
|
<li>The diffusion, as one rectangle that covers both the <tt class="docutils literal">LCW</tt> and the <tt class="docutils literal">RCW</tt> (<tt class="docutils literal">RDS_NDIF</tt>).</li>
|
|
<li>The active area (<tt class="docutils literal">RDS_ACTIV</tt>).</li>
|
|
<li>The N implantation (<tt class="docutils literal">RDS_NIMP</tt>).</li>
|
|
</ol>
|
|
<p>In the layout send to the foundry, the source & drain are draw as one rectangle
|
|
across the gate area (the transistor being defined by the intersection of both
|
|
rectangles).</p>
|
|
</li>
|
|
</ul>
|
|
<p></p>
|
|
</div>
|
|
<div class="section" id="the-mbk-to-rds-via-table">
|
|
<h3><a class="toc-backref" href="#id9">The <tt class="docutils literal">MBK_TO_RDS_VIA</tt> table</a></h3>
|
|
<p>This table is to translate <em>default</em> VIAs into real via. In the symbolic layout
|
|
the default VIA is simply a point and a set of layers. All layers are converted
|
|
in squares shapes centered on the VIA coordinate. The one dimension given is the
|
|
size of the side of that square.</p>
|
|
<p>Note that although we are refering to VIAs, which for the purists are between two
|
|
metal layers, this table also describe <em>contacts</em>.</p>
|
|
<p>Example:</p>
|
|
<pre class="literal-block">
|
|
TABLE MBK_TO_RDS_VIA
|
|
|
|
CONT_DIF_P RDS_PDIF 0.54 ALL \
|
|
RDS_CONT 0.18 ALL \
|
|
RDS_ALU1 0.36 ALL \
|
|
RDS_ACTIV 0.54 DRC \
|
|
RDS_PIMP 0.90 DRC
|
|
|
|
CONT_POLY RDS_POLY 0.54 ALL \
|
|
RDS_CONT 0.18 ALL \
|
|
RDS_ALU1 0.36 ALL
|
|
|
|
CONT_VIA RDS_ALU1 0.45 ALL \
|
|
RDS_VIA1 0.27 ALL \
|
|
RDS_ALU2 0.45 ALL
|
|
|
|
END
|
|
</pre>
|
|
<div class="admonition note">
|
|
<p class="first admonition-title">Note</p>
|
|
<p class="last"><strong>In CONT_DIF_P</strong> you may see that only three layers will be shown under
|
|
<tt class="docutils literal">graal</tt>, but five will be generated in the <tt class="docutils literal">gds</tt> layout.</p>
|
|
</div>
|
|
</div>
|
|
<div class="section" id="the-mbk-to-rds-bigvia-hole-table">
|
|
<h3><a class="toc-backref" href="#id10">The <tt class="docutils literal">MBK_TO_RDS_BIGVIA_HOLE</tt> table</a></h3>
|
|
<p>In <span class="cb">s2r</span>, when generating BIGVIAs, the matrix of holes they contains is
|
|
not draw relative to the position of the BIGVIA itself, but on a grid which
|
|
is common througout all the design real layout. This is to allow overlap
|
|
between two BIGVIA without risking the holes matrix to be not exactly overlapping.
|
|
As a consequence, when visualizing the <tt class="docutils literal">gds</tt> file, the holes may not be centerend
|
|
inside one individual BIGVIA.</p>
|
|
<p>The <tt class="docutils literal">MBK_TO_RDS_BIGVIA_HOLE</tt> table define the global hole matrix for the whole
|
|
design. The first number is the individual hole side and the second the grid step
|
|
(edge to edge). The figure below show the hole generation.</p>
|
|
<p> <img alt="BIGVIA holes" class="align-middle" src="../pages/images/bigvia-1.png" style="width: 40%;" /> </p>
|
|
<p>Example of BIGVIA overlap:</p>
|
|
<p> <img alt="BIGVIA holes overlap" class="align-middle" src="../pages/images/bigvia-2.png" style="width: 40%;" /> </p>
|
|
<p>Example:</p>
|
|
<pre class="literal-block">
|
|
TABLE MBK_TO_RDS_BIGVIA_HOLE
|
|
|
|
CONT_VIA RDS_VIA1 0.27 0.27 ALL
|
|
CONT_VIA2 RDS_VIA2 0.27 0.27 ALL
|
|
CONT_VIA3 RDS_VIA3 0.27 0.27 ALL
|
|
CONT_VIA4 RDS_VIA4 0.27 0.27 ALL
|
|
CONT_VIA5 RDS_VIA5 0.36 0.36 ALL
|
|
|
|
END
|
|
</pre>
|
|
<div class="admonition note">
|
|
<p class="first admonition-title">Note</p>
|
|
<p class="last"><strong>BIGVIA demotion.</strong> If the size of the bigvia is too small, there is
|
|
a possibility that no hole from the global matrix will be under it.
|
|
To avoid that case, if the either side of the BIGVIA is less than
|
|
<tt class="docutils literal">1.5 * step</tt>, the BIGVIA is demoted to a simple VIA.</p>
|
|
</div>
|
|
</div>
|
|
<div class="section" id="the-mbk-to-rds-bigvia-metal-table">
|
|
<h3><a class="toc-backref" href="#id11">The <tt class="docutils literal">MBK_TO_RDS_BIGVIA_METAL</tt> table</a></h3>
|
|
<p>This table describe how the metal part of a BIGVIA is expanded (for the hole
|
|
part, see the previous table <tt class="docutils literal">MBK_TO_RDS_BIGVIA_HOLE</tt>). The rule give for each
|
|
metal:</p>
|
|
<ol class="arabic simple">
|
|
<li>The <em>delta-with</em> (have to ask Franck).</li>
|
|
<li>The <em>overhang</em>, the length the real rectangle is expanded on each side from
|
|
the symbolic rectange.</li>
|
|
</ol>
|
|
<p>Example:</p>
|
|
<pre class="literal-block">
|
|
TABLE MBK_TO_RDS_BIGVIA_METAL
|
|
|
|
CONT_VIA RDS_ALU1 0.0 0.09 ALL \
|
|
RDS_ALU2 0.0 0.09 ALL
|
|
|
|
CONT_VIA2 RDS_ALU2 0.0 0.09 ALL \
|
|
RDS_ALU3 0.0 0.09 ALL
|
|
|
|
CONT_VIA3 RDS_ALU3 0.0 0.09 ALL \
|
|
RDS_ALU4 0.0 0.09 ALL
|
|
|
|
CONT_VIA4 RDS_ALU4 0.0 0.09 ALL \
|
|
RDS_ALU5 0.0 0.09 ALL
|
|
|
|
CONT_VIA5 RDS_ALU5 0.0 0.09 ALL \
|
|
RDS_ALU6 0.0 0.18 ALL
|
|
END
|
|
</pre>
|
|
</div>
|
|
<div class="section" id="the-mbk-wiresetting-table">
|
|
<h3><a class="toc-backref" href="#id12">The <tt class="docutils literal">MBK_WIRESETTING</tt> table</a></h3>
|
|
<p>From a strict standpoint this table shouldn't be here but put in a separate
|
|
configuration file, because it contains informations only used by the symbolic
|
|
layout tools (<tt class="docutils literal">ocp</tt>, <tt class="docutils literal">nero</tt>, <tt class="docutils literal">ring</tt>).</p>
|
|
<p>This table defines the cell gauge the routing pitch and minimal (symbolic)
|
|
wire width and minimal spacing for the routers. They are patly redundant.</p>
|
|
<p>Example:</p>
|
|
<pre class="literal-block">
|
|
TABLE MBK_WIRESETTING
|
|
|
|
X_GRID 10
|
|
Y_GRID 10
|
|
Y_SLICE 100
|
|
WIDTH_VDD 12
|
|
WIDTH_VSS 12
|
|
TRACK_WIDTH_ALU8 0
|
|
TRACK_WIDTH_ALU7 4
|
|
TRACK_WIDTH_ALU6 4
|
|
TRACK_WIDTH_ALU5 4
|
|
TRACK_WIDTH_ALU4 3
|
|
TRACK_WIDTH_ALU3 3
|
|
TRACK_WIDTH_ALU2 3
|
|
TRACK_WIDTH_ALU1 3
|
|
TRACK_SPACING_ALU8 0
|
|
TRACK_SPACING_ALU7 4
|
|
TRACK_SPACING_ALU6 4
|
|
TRACK_SPACING_ALU5 4
|
|
TRACK_SPACING_ALU4 4
|
|
TRACK_SPACING_ALU3 4
|
|
TRACK_SPACING_ALU2 4
|
|
TRACK_SPACING_ALU1 3
|
|
|
|
END
|
|
</pre>
|
|
</div>
|
|
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