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coriolis/cumulus/src/designflow
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Jean-Paul Chaput 4398770432 Add SystemVerilog support to designflow.yosys. Merge with YosysNp. 
* New: In designflow.yosys, add support to load SystemVerilog with the
    synlig plugin (CHIPS Alliance).
      Integrate back the "non-Python" version of the task. Now switch
    automatically between Python & Non-Python based on the availability
    of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
    dependency file to be used as the default target. Now use the
    "top module" argument.
 		2023-09-16 18:12:10 +02:00
..
__init__.py Add DoIt base design flow support. In full replacement of Makefiles. 2022-12-31 15:01:37 +01:00
alias.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
alliancesynth.py Add DoIt base design flow support. In full replacement of Makefiles. 2022-12-31 15:01:37 +01:00
asimut.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
blif2vst.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
boog.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
boom.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
clean.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
command.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
copy.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
cougar.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
dreal.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
druc.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
flatph.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
genpat.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
graal.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
klayout.py Fix: designflow/klayout.py rule forgot to add targets. 2023-03-07 11:52:52 +01:00
loon.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
lvx.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
pnr.py Create stub for Tramontana, reimplementation of the extractor/LVX. 2023-03-16 15:06:11 +01:00
pnrcheck.py Just a little indentation for my autistic self. 2023-01-09 09:21:56 +01:00
routecheck.py Add DoIt base design flow support. In full replacement of Makefiles. 2022-12-31 15:01:37 +01:00
s2r.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
sv2v.py Add SystemVerilog support to designflow.yosys. Merge with YosysNp. 2023-09-16 18:12:10 +02:00
svase.py Add SystemVerilog support to designflow.yosys. Merge with YosysNp. 2023-09-16 18:12:10 +02:00
task.py In designflow, re-export LD_LIBRARY_PATH only if there is an ALLIANCE_TOP. 2023-06-25 11:53:26 +02:00
technos.py Add support for GF180MCU, borrowed from Chips4Makers. 2023-08-31 16:14:08 +02:00
vasy.py Add basic yosys (nopy), klayout scripts and command support to designflow. 2023-03-01 23:57:55 +01:00
yosys.py Add SystemVerilog support to designflow.yosys. Merge with YosysNp. 2023-09-16 18:12:10 +02:00
yosysnp.py Add SystemVerilog support to designflow.yosys. Merge with YosysNp. 2023-09-16 18:12:10 +02:00