660 lines
32 KiB
Python
660 lines
32 KiB
Python
# -*- Mode:Python -*-
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#
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# This file is part of the Coriolis Software.
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# Copyright (c) Sorbonne Université 2016-2021, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | B o r a - A n a l o g S l i c i n g T r e e |
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# | |
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# | Author : Jean-Paul Chaput |
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# | E-mail : Jean-Paul.Chaput@lip6.fr |
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# | =============================================================== |
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# | Python : "./karakaze/AnalogDesign.py" |
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# +-----------------------------------------------------------------+
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from Hurricane import *
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from Hurricane import DataBase
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import CRL
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import helpers
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from helpers import isderived, trace
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from helpers.io import ErrorMessage as Error
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from Analog import Device, TransistorFamily, Transistor, \
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CommonDrain, CommonGatePair, CommonSourcePair, \
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CrossCoupledPair, DifferentialPair, LevelShifter, \
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SimpleCurrentMirror, CapacitorFamily, \
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MultiCapacitor, CapacitorFamily, MultiCapacitor, \
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ResistorFamily, Resistor, LayoutGenerator, \
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Matrix
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from Bora import ParameterRange, StepParameterRange, \
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MatrixParameterRange, SlicingNode, HSlicingNode, \
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VSlicingNode, DSlicingNode, RHSlicingNode, \
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RVSlicingNode
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import karakaze.oceane
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import Anabatic
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import Katana
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import Bora
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#helpers.setTraceLevel( 100 )
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NMOS = Transistor.NMOS
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PMOS = Transistor.PMOS
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PIP = CapacitorFamily.PIP
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MIM = CapacitorFamily.MIM
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MOM = CapacitorFamily.MOM
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LOWRES = ResistorFamily.LOWRES
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HIRES = ResistorFamily.HIRES
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RPOLYH = ResistorFamily.RPOLYH
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RPOLY2PH = ResistorFamily.RPOLY2PH
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Center = SlicingNode.AlignCenter
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Left = SlicingNode.AlignLeft
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Right = SlicingNode.AlignRight
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Top = SlicingNode.AlignTop
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Bottom = SlicingNode.AlignBottom
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Unknown = SlicingNode.AlignBottom
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VNode = 1
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HNode = 2
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DNode = 3
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def toDbU ( value ): return DbU.fromPhysical( value, DbU.UnitPowerMicro )
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def toLength ( value ): return float(value) * 1e+6
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def readMatrix ( rows ):
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if not isinstance(rows,list):
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print( '[ERROR] readMatrix(): First level is not a list.' )
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sys.exit( 1 )
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rowCount = len(rows)
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for row in range(len(rows)):
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column = rows[row]
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if not isinstance(column,list):
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print( '[ERROR] readMatrix(): Column {} is not a list.'.format(row) )
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sys.exit( 1 )
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if row == 0:
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columnCount = len(column)
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matrix = Matrix( rowCount, columnCount )
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else:
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if columnCount != len(column):
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print( '[ERROR] readMatrix(): Column {} size discrepency (sould be {}).'.format(len(column),columnCount))
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sys.exit( 1 )
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for column in range(len(column)):
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matrix.setValue( row, column, rows[row][column] )
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return matrix
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class AnalogDesign ( object ):
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def __init__ ( self ):
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self.cellName = None
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self.netCache = {}
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self.rg = None
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self.library = None
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self.cell = None
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self.netCache = {}
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self.slicingTree = None
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self.stack = []
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self.stack2 = []
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self.toleranceRatioH = 0
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self.toleranceRatioW = 0
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self.toleranceBandH = 0
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self.toleranceBandW = 0
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self.parameters = karakaze.oceane.Parameters()
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return
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def setCellName ( self, name ):
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self.cellName = name
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return
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def beginCell ( self, cellName ):
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self.setCellName( cellName )
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UpdateSession.open()
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self.rg = CRL.AllianceFramework.get().getRoutingGauge()
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self.cell = CRL.AllianceFramework.get().createCell( self.cellName )
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self.library = Library.create( DataBase.getDB().getRootLibrary(), 'AnalogRootLibrary' )
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self.generator = LayoutGenerator()
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return
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def endCell ( self ):
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UpdateSession.close()
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return
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def checkBeginCell ( self, function ):
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if not self.cell:
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raise Error( 3, [ 'AnalogDesign: \"AnalogDevice.beginCell()\" must be called *before* \"%s\".' \
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% function
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] )
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return
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def checkConnexion ( self, count, net, connexion ):
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if not isinstance(connexion,tuple):
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raise Error( 3, [ 'AnalogDesign.doNets(): \"self.netSpecs\" in \"%s\", connexion [%d] is *not* a tuple.' \
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% (net.getName(),count)
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, '%s' % str(connexion) ] )
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if len(connexion) != 2:
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raise Error( 3, [ 'AnalogDesign.doNets(): \"self.devicesSpecs\" in \"%s\", connexion [%d] has %d items instead of 2 .' \
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% (net.getName(),count,len(connexion))
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, '%s' % str(connexion) ] )
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if not isinstance(connexion[0],str):
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raise Error( 3, [ 'AnalogDesign.doNets(): \"self.devicesSpecs\" in \"%s\", connexion [%d], field [0] (instance) is *not* a string.' \
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% (net.getName(),count)
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, '%s' % str(connexion) ] )
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if not isinstance(connexion[1],str):
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raise Error( 3, [ 'AnalogDesign.doNets(): \"self.devicesSpecs\" in \"%s\", connexion [%d], field [1] (terminal) is *not* a string.' \
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% (net.getName(),count)
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, '%s' % str(connexion) ] )
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return
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def checkRail( self, net, metal, npitch, cellName, instanceName ):
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#Net verification missing
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if not isinstance(metal,str):
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raise Error( 3, [ 'AnalogDesign.checkRail(): \"metal\" is *not* a string.' ] )
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if not isinstance(npitch,int):
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raise Error( 3, [ 'AnalogDesign.checkRail(): \"NPitch\" is *not* an int.' ] )
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if not isinstance(cellName,str):
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raise Error( 3, [ 'AnalogDesign.checkRail(): \"cellName\" is *not* a string.' ] )
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if not isinstance(instanceName,str):
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raise Error( 3, [ 'AnalogDesign.checkRail(): \"instanceName\" is *not* a string.' ] )
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return
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def connect ( self, instanceName, masterNetName, net ):
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instance = getattr( self, instanceName )
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masterNet = instance.getMasterCell().getNet( masterNetName )
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instance.getPlug( masterNet ).setNet( net )
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state = NetRoutingExtension.get(net)
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device = instance.getMasterCell()
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if masterNetName=='B':
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device.getParameter('B.w').setValue(int(state.getWPitch()))
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if masterNetName=='G':
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device.getParameter('G.w').setValue(int(state.getWPitch()))
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if masterNetName=='G1':
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device.getParameter('G1.w').setValue(int(state.getWPitch()))
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if masterNetName=='G2':
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device.getParameter('G2.w').setValue(int(state.getWPitch()))
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if masterNetName=='D':
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device.getParameter('D.w').setValue(int(state.getWPitch()))
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if masterNetName=='D1':
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device.getParameter('D1.w').setValue(int(state.getWPitch()))
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if masterNetName=='D2':
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device.getParameter('D2.w').setValue(int(state.getWPitch()))
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if masterNetName=='S':
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device.getParameter('S.w').setValue(int(state.getWPitch()))
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return
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def getNet ( self, netName, create=True ):
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net = None
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if netName in self.netCache:
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net = self.netCache[netName]
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elif create:
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net = Net.create( self.cell, netName )
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self.netCache[ netName ] = net
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return net
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def doNets ( self ):
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self.checkBeginCell( 'AnalogDesign.doNets()' )
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if not hasattr(self,'netSpecs'):
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raise Error( 3, 'AnalogDesign.doNets(): Mandatory attribute \"self.netSpecs\" has not been defined.' )
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if not isinstance(self.netSpecs,dict):
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raise Error( 3, 'AnalogDesign.doNets(): Attribute \"self.netSpecs\" *must* be a Python dict.' )
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for netName, netType in self.netTypes.items():
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if not isinstance(netName,str):
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raise Error( 3, 'AnalogDesign.doNets(): Dict key (net name) of \"self.netTypes\" *must* be a string (%s).' % str(netName) )
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net = self.getNet( netName )
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isExternal = False
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if 'isExternal' in netType: isExternal = netType['isExternal']
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for netName, connexions in self.netSpecs.items():
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if not isinstance(netName,str):
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raise Error( 3, 'AnalogDesign.doNets(): Dict key (net name) of \"self.netSpecs\" *must* be a string (%s).' % str(netName) )
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net = self.getNet( netName )
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state = NetRoutingExtension.create( net, NetRoutingState.AutomaticGlobalRoute|NetRoutingState.Analog )
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count = 1
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for connexion in connexions:
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if isinstance(connexion,tuple):
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self.checkConnexion( count, net, connexion )
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self.connect( connexion[0], connexion[1], net )
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count += 1
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else:
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if isinstance(connexion,dict): state.setWPitch(long(connexion['W']))
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return
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def checkDSpec ( self, count, dspec ):
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if not isinstance(dspec,list):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], is *not* a list.' % count
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, '%s' % str(dspec) ])
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if not isderived(dspec[0],Device):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [0] is *not* a Device class.' % count
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, '%s' % str(dspec) ])
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specSize = 0
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if isderived(dspec[0],TransistorFamily): specSize = 12
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elif isderived(dspec[0], CapacitorFamily): specSize = 7
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elif isderived(dspec[0], ResistorFamily): specSize = 8
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], has unsupported device type.' \
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% (count)
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, '%s' % str(dspec) ])
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if len(dspec) < specSize:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], has %d items instead of 12 .' \
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% (count,len(dspec))
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, '%s' % str(dspec) ])
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if not isinstance(dspec[1],str):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [1] (model name) is *not* a string.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[2],str):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [2] (layout style) is *not* a string.' % count
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, '%s' % str(dspec) ])
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if isderived(dspec[0],TransistorFamily):
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if dspec[3] not in [NMOS, PMOS]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either NMOS or PMOS.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[4],float):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (WE) is *not* a float.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[5],float):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [5] (LE) is *not* a float.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[6],int):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [6] (M) is *not* an int.' % count
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, '%s' % str(dspec) ])
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if (not dspec[7] is None) and (not isinstance(dspec[7],int)):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [7] (Mint) is neither an int nor None.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[8],int):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [8] (external dummies) is *not* an int.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[9],bool):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [9] (source first) is *not* a boolean.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[10],int):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [10] (bulk) is *not* an int.' % count
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, '%s' % str(dspec) ])
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else:
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if dspec[10] > 0xf:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [10] (bulk) is greater than 0xf.' % count
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, '%s' % str(dspec) ])
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if not isinstance(dspec[11],bool):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [11] (bulk connected) is *not* a boolean.' % count
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, '%s' % str(dspec) ])
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elif isderived(dspec[0], CapacitorFamily):
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if dspec[3] not in [PIP, MIM, MOM]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either PIP, MIM or MOM.' % count
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, '%s' % str(dspec) ])
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if isinstance(dspec[4],float): pass
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elif isinstance(dspec[4],tuple): pass
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (Cs) should either be *one* float or a *list* of floats.' % count
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, '%s' % str(dspec) ])
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elif isderived(dspec[0],ResistorFamily):
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if dspec[3] not in [RPOLYH, RPOLY2PH]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either RPOLYH or RPOLY2PH.' % count
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, '%s' % str(dspec) ])
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if isinstance(dspec[5],float): pass
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (resistance) must be a float.' % count
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, '%s' % str(dspec) ])
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], spec list do not match any known pattern.' % count
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, '%s' % str(dspec) ])
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return
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def checkDSpecDigital ( self, count, dspec ):
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# if not isinstance(dspec[0],str):
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# raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [0] (model name) is *not* a string.' % count
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# , '%s' % str(dspec) ])
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if not isinstance(dspec[1],str):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [1] (model name) is *not* a string.' % count
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, '%s' % str(dspec) ])
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return
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def readParameters ( self, path ):
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trace( 110, ',+', '\tReading Oceane parameters from \"%s\"\n' % path )
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if not path: return
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self.parameters.read( path );
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for dspec in self.devicesSpecs:
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if isinstance(dspec[0],Cell):
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pass
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elif issubclass(dspec[0],TransistorFamily):
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Tname = dspec[1].split('_')[0]
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Tparameters = self.parameters.getTransistor( Tname )
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if not Tparameters:
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raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for \"%s\".' % Tname ] )
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continue
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dspec[4] = toLength( Tparameters.W )
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dspec[5] = toLength( Tparameters.L )
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dspec[6] = Tparameters.M
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trace( 110, '\t- \"%s\" : W:%f L:%f M:%d\n' % (Tname
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,dspec[4]
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,dspec[5]
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,dspec[6]) )
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elif issubclass(dspec[0],CapacitorFamily):
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Cname = dspec[1]
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Cparameters = self.parameters.getCapacitor( Cname )
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if not Cparameters:
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raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for capacity \"%s\".' % Cname ] )
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continue
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dspec[4] = Cparameters.C * 1e+12
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trace( 110, '\t- \"%s\" : C:%fpF\n' % (Cname ,dspec[4]) )
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elif issubclass(dspec[0],ResistorFamily):
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print( WarningMessage( 'Resistor devices are not supported yet by Oceane parser (instance:"{}").'.format(dspec[1]) ))
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else:
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print( WarningMessage( 'Unsupported analog device type {0} (instance:"{1}").'.format(dspec[0],dspec[1]) ))
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trace( 110, '-,' )
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return
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def doDevice ( self, count, dspec ):
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self.checkBeginCell( 'AnalogDesign.doDevice()' )
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if len(dspec) == 2:
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self.checkDSpecDigital( count, dspec )
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if isinstance( dspec[0], str ):
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masterCell = CRL.AllianceFramework.get().getCell( dspec[0], CRL.Catalog.State.Views )
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instance = Instance.create( self.cell
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, dspec[1]
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, masterCell
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, Transformation()
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, Instance.PlacementStatus.UNPLACED )
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self.__dict__[ dspec[1] ] = instance
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else:
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masterCell = dspec[0]
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instance = Instance.create( self.cell
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, dspec[1]
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, masterCell
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, Transformation()
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, Instance.PlacementStatus.UNPLACED )
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self.__dict__[ dspec[1] ] = instance
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else:
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self.checkDSpec( count, dspec )
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trace( 110, '\t==============================================================\n' )
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trace( 110, '\tBuilding \"%s\"\n' % dspec[1] )
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if isderived(dspec[0],TransistorFamily):
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device = dspec[0].create( self.library, dspec[1], dspec[3], dspec[11] )
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device.getParameter( 'Layout Styles' ).setValue( dspec[2] )
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device.getParameter( 'W' ).setValue( toDbU(dspec[4]) )
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device.getParameter( 'L' ).setValue( toDbU(dspec[5]) )
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device.getParameter( 'M' ).setValue( dspec[6] )
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device.setSourceFirst( dspec[9] )
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device.setBulkType ( dspec[10] )
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if (len(dspec) > 12): device.getParameter( 'NERC' ).setValue(int (dspec[12]))
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if (len(dspec) > 13): device.getParameter( 'NIRC' ).setValue(int (dspec[13]))
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if (len(dspec) > 14):
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for wiringSpec in dspec[14].split(' '):
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fields = wiringSpec.split('.')
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if len(fields) > 1:
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device.getParameter( fields[0]+'.t' ).setValue( fields[1] )
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if not (dspec[7] is None): device.setMint ( dspec[7] )
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if dspec[8]: device.setExternalDummy( dspec[8] )
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elif isderived(dspec[0],CapacitorFamily):
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if isinstance(dspec[4],float): capaValues = (dspec[4],)
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elif isinstance(dspec[4],tuple): capaValues = dspec[4]
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else:
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raise ErrorMessage( 1, 'AnalogDesign.doDevice(): Invalid type for capacities values "%s".' \
|
|
% str(dspec[4]) )
|
|
|
|
device = dspec[0].create( self.library, dspec[1], dspec[3], len(capaValues) )
|
|
device.getParameter( 'Layout Styles' ).setValue( dspec[2] )
|
|
device.getParameter( 'matrix' ).setMatrix( dspec[5] )
|
|
device.setDummy( dspec[6] )
|
|
for i in range(len(capaValues)):
|
|
device.getParameter( 'capacities' ).setValue( i, capaValues[i] )
|
|
|
|
elif isderived(dspec[0],ResistorFamily):
|
|
print( dspec )
|
|
device = dspec[0].create( self.library, dspec[1], dspec[3] )
|
|
device.getParameter( 'R' ).setValue( dspec[4] )
|
|
device.getParameter( 'W' ).setValue( toDbU(dspec[5]) )
|
|
device.getParameter( 'L' ).setValue( toDbU(dspec[6]) )
|
|
device.getParameter( 'bends' ).setValue( dspec[7] )
|
|
trace( 100, '\tW:{0}\n'.format(dspec[5]) )
|
|
trace( 100, '\tpW:{0}\n'.format(device.getParameter('W')) )
|
|
trace( 100, '\tbends:{0}\n'.format(dspec[7]) )
|
|
else:
|
|
raise ErrorMessage( 1, 'AnalogDesign.doDevice(): Unknown/unsupported device "%s".' % str(dspec[0]) )
|
|
|
|
self.generator.setDevice ( device )
|
|
self.generator.drawLayout()
|
|
instance = Instance.create( self.cell
|
|
, dspec[1]
|
|
, device
|
|
, Transformation()
|
|
, Instance.PlacementStatus.UNPLACED )
|
|
|
|
self.__dict__[ dspec[1] ] = instance
|
|
trace( 100, '\tAdd Instance:{0}\n'.format(dspec[1]) )
|
|
return
|
|
|
|
def doDevices ( self ):
|
|
trace( 110, ',+', '\tAnalogDesign.doDevices()\n' )
|
|
|
|
if not hasattr(self,'devicesSpecs'):
|
|
raise Error( 3, 'AnalogDesign.doDevices(): Mandatory attribute \"self.devicesSpecs\" has not been defined.' )
|
|
if not isinstance(self.devicesSpecs,list):
|
|
raise Error( 3, 'AnalogDesign.doDevices(): Attribute \"self.devicesSpecs\" *must* be a Python list.' )
|
|
|
|
count = 1
|
|
for dspec in self.devicesSpecs:
|
|
self.doDevice( count, dspec )
|
|
count += 1
|
|
trace( 110, '-,' )
|
|
return
|
|
|
|
def showNode ( self, node ):
|
|
lines = [ '{' ]
|
|
for key, value in node.items():
|
|
if key == 'children':
|
|
lines += [ "%20s { ... }" % "'children':" ]
|
|
else:
|
|
skey = "'%s':" % str(key)
|
|
lines += [ "%20s %s" % (skey,str(value)) ]
|
|
lines += [ '}' ]
|
|
return lines
|
|
|
|
def checkNode ( self, node, isRoot ):
|
|
if not isinstance(node,dict):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Node element is *not* a dict.'
|
|
] + self.showNode(node) )
|
|
if not 'type' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"type\" key/element.'
|
|
] + self.showNode(node) )
|
|
nodeType = node['type']
|
|
if nodeType not in [VNode, HNode, DNode]:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"type\" must be one of VNode, HNode or DNode.'
|
|
] + self.showNode(node) )
|
|
|
|
if nodeType == DNode:
|
|
if not 'device' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"device\" key/element.'
|
|
] + self.showNode(node) )
|
|
if not isinstance(node['device'],str):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"device\" value *must* be of type str.'
|
|
] + self.showNode(node) )
|
|
if not 'span' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"span\" key/element.'
|
|
] + self.showNode(node) )
|
|
if not isinstance(node['span'],tuple) \
|
|
or len(node['span']) != 3 \
|
|
or not isinstance(node['span'][0],float) \
|
|
or not isinstance(node['span'][1],float) \
|
|
or not isinstance(node['span'][2],float):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"span\" value *must* be a tuple of 3 floats.'
|
|
] + self.showNode(node) )
|
|
if not 'NF' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"NF\" key/element.'
|
|
] + self.showNode(node) )
|
|
if not isinstance(node['NF'],int):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"NF\" value *must* be of type int.'
|
|
] + self.showNode(node) )
|
|
else:
|
|
if isRoot:
|
|
if not 'toleranceRatioH' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"toleranceRationH\" key/element in root node.'
|
|
] + self.showNode(node) )
|
|
if not 'toleranceRatioW' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"toleranceRationW\" key/element in root node.'
|
|
] + self.showNode(node) )
|
|
if not 'toleranceBandH' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"toleranceBandH\" key/element in root node.'
|
|
] + self.showNode(node) )
|
|
if not 'toleranceBandW' in node:
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): Missing mandatory \"toleranceBandW\" key/element in root node.'
|
|
] + self.showNode(node) )
|
|
if not 'children' in node:
|
|
print( Error( 3, [ 'AnalogDesign.doSlicingTree(): Suspicious root node without children.'
|
|
] + self.showNode(node) ))
|
|
if 'children' in node:
|
|
if not isinstance(node['children'],list):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"children\" value *must* be of type list.' ]
|
|
+ self.showNode(node) )
|
|
|
|
if 'symmetries' in node:
|
|
symmetries = node['symmetries']
|
|
if not isinstance(symmetries,list):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"symmetries\" value *must* be of type list.'
|
|
] + self.showNode(node) )
|
|
for i in range(len(symmetries)):
|
|
if not isinstance(symmetries[i],tuple) \
|
|
or len(symmetries[i]) != 2 \
|
|
or not isinstance(symmetries[i][0],int) \
|
|
or not isinstance(symmetries[i][1],int):
|
|
raise Error( 3, [ 'AnalogDesign.doSlicingTree(): \"symmetries\" entry [%d] *must* be a tuple of 2 int.' % i ]
|
|
+ self.showNode(node) )
|
|
return
|
|
|
|
def beginSlicingTree ( self ):
|
|
trace( 110, ',+', '\tAnalogDesign.beginSlicingTree()\n' )
|
|
return
|
|
|
|
def topNode ( self ): return self.stack[-1][0]
|
|
def topSymmetries ( self ): return self.stack[-1][1]
|
|
def topSymmetriesNet ( self ): return self.stack[-1][2]
|
|
|
|
def setToleranceRatioH ( self, u ): self.toleranceRatioH = toDbU(u)
|
|
def setToleranceRatioW ( self, u ): self.toleranceRatioW = toDbU(u)
|
|
def setToleranceBandH ( self, u ): self.toleranceBandH = toDbU(u)
|
|
def setToleranceBandW ( self, u ): self.toleranceBandW = toDbU(u)
|
|
|
|
def dupTolerances ( self, node ):
|
|
node.setToleranceRatioH( self.toleranceRatioH )
|
|
node.setToleranceRatioW( self.toleranceRatioW )
|
|
node.setToleranceBandH ( self.toleranceBandH )
|
|
node.setToleranceBandW ( self.toleranceBandW )
|
|
return
|
|
|
|
def pushNode ( self, node ):
|
|
trace( 110, ',+', '\tSlicingTree.pushNode() %s ' % str(node) )
|
|
parent = None
|
|
if len(self.stack):
|
|
parent = self.topNode()
|
|
parent.push_back( node )
|
|
trace( 110, '(parent id:%d)\n' % parent.getId() )
|
|
else:
|
|
trace( 110, '(Root)\n' )
|
|
self.slicingTree = node
|
|
node.setCell( self.cell )
|
|
|
|
self.stack.append( (node,[],[]) )
|
|
self.dupTolerances( node )
|
|
node.setRoutingGauge( self.rg )
|
|
#node.cprint()
|
|
return
|
|
|
|
def pushVNode ( self, alignment ):
|
|
self.pushNode( VSlicingNode.create( alignment ) )
|
|
return
|
|
|
|
def pushHNode ( self, alignment ):
|
|
self.pushNode( HSlicingNode.create( alignment ) )
|
|
return
|
|
|
|
def popNode ( self ):
|
|
for childIndex, copyIndex in self.topSymmetries():
|
|
self.topNode().addSymmetry( childIndex, copyIndex )
|
|
for type, net1, net2 in self.topSymmetriesNet():
|
|
if (net2 == None):
|
|
self.topNode().addSymmetryNet( type, net1 )
|
|
else:
|
|
self.topNode().addSymmetryNet( type, net1, net2 )
|
|
|
|
trace( 110, '-,', '\tSlicingTree.popNode() %s\n' % str(self.topNode()) )
|
|
if len(self.stack) == 1:
|
|
trace( 110, '\tAnalogDesign.endSlicingTree()\n' )
|
|
trace( 110, '-,', '\tSlicingTree %s stack size:%d\n' % (self.cell.getName(), len(self.stack)) )
|
|
#self.topNode().setCell( self.cell )
|
|
self.topNode().updateNetConstraints()
|
|
self.topNode().updateGlobalSize()
|
|
del self.stack[-1]
|
|
return
|
|
|
|
def addDevice ( self, name, align, parameter=None, index=0 ):
|
|
node = DSlicingNode.create( name, self.cell, parameter, self.rg )
|
|
node.setAlignment( align )
|
|
if index != 0: node.setBoxSetIndex( index )
|
|
self.topNode().push_back( node )
|
|
trace( 110, '\tSlicingTree.addDevice() %s (parent id:%d)\n' % (str(node),self.topNode().getId()) )
|
|
#node.cprint()
|
|
return
|
|
|
|
def addHRail ( self, net, metal, npitch, cellName, instanceName ):
|
|
self.checkRail( net, metal, npitch, cellName, instanceName )
|
|
node = RHSlicingNode.create( net, DataBase.getDB().getTechnology().getLayer(metal), npitch, cellName, instanceName)
|
|
self.topNode().push_back( node )
|
|
trace( 110, '\tSlicingTree.addHRail() to %s\n' % (str(self.topNode())) )
|
|
#node.cprint()
|
|
return
|
|
|
|
def addVRail ( self, net, metal, npitch, cellName, instanceName ):
|
|
self.checkRail( net, metal, npitch, cellName, instanceName )
|
|
node = RVSlicingNode.create( net, DataBase.getDB().getTechnology().getLayer(metal), npitch, cellName, instanceName)
|
|
self.topNode().push_back( node )
|
|
trace( 110, '\tSlicingTree.addVRail() to %s\n' % (str(self.topNode())) )
|
|
#node.cprint()
|
|
return
|
|
|
|
def addSymmetry ( self, childIndex, copyIndex ):
|
|
self.topSymmetries().append( (childIndex,copyIndex) )
|
|
return
|
|
|
|
def addSymmetryNet ( self, type, net1, net2=None ):
|
|
self.topSymmetriesNet().append( (type, net1, net2) )
|
|
return
|
|
|
|
def endSlicingTree ( self ):
|
|
self.slicingTree.updateGlobalSize()
|
|
#bora = Bora.BoraEngine.get( self.cell )
|
|
#if not bora: bora = Bora.BoraEngine.create( self.cell )
|
|
#bora.updateSlicingTree()
|
|
return
|
|
|
|
def updatePlacement ( self, *args ):
|
|
if self.slicingTree:
|
|
bora = Bora.BoraEngine.get( self.cell )
|
|
if not bora: bora = Bora.BoraEngine.create( self.cell )
|
|
|
|
signatureMatched = True
|
|
if len(args) == 2: bora.updatePlacement( toDbU(args[0]), toDbU(args[1]) )
|
|
elif len(args) == 1: bora.updatePlacement( args[0] )
|
|
else: signatureMatched = False
|
|
|
|
#if signatureMatched:
|
|
# katana = Katana.KatanaEngine.get( self.cell )
|
|
# if katana:
|
|
# katana.loadGlobalRouting( Anabatic.EngineLoadGrByNet )
|
|
# katana.runNegociate( Katana.Flags.PairSymmetrics );
|
|
# #katana.destroy()
|
|
return
|