955 lines
82 KiB
TeX
955 lines
82 KiB
TeX
\hypertarget{openchams_openChamsPres}{}\section{Presentation}\label{openchams_openChamsPres}
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The {\bfseries Open\-C\-H\-A\-M\-S} format was developped as a part of the Chams Project (\href{http://www-soc.lip6.fr/recherche/cian/chams/}{\tt http\-://www-\/soc.\-lip6.\-fr/recherche/cian/chams/}). It aims at offering a convenient way to describe analogic circuits' netlists and is based on X\-M\-L. Some C\-H\-A\-M\-S specific informations, such as schematic properties, layout properties or sizing procedure, can be described in this format.\par
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\hypertarget{openchams_openChamsAutrhos}{}\subsection{Author}\label{openchams_openChamsAutrhos}
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Damien Dupuis\-: damien.\-dupuis(at)lip6(.)fr\hypertarget{openchams_openChamsDB}{}\section{Stand alone database structure}\label{openchams_openChamsDB}
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The database has many objects that can be arranged in five categories\-:
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\begin{DoxyItemize}
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\item General
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\begin{DoxyItemize}
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\item \hyperlink{class_open_chams_1_1_circuit}{Open\-Chams\-::\-Circuit}
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\item Open\-Chams\-::\-Name
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\item \hyperlink{class_open_chams_1_1_open_chams_exception}{Open\-Chams\-::\-Open\-Chams\-Exception}
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\end{DoxyItemize}
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\item Netlist
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\begin{DoxyItemize}
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\item \hyperlink{class_open_chams_1_1_netlist}{Open\-Chams\-::\-Netlist}
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\item \hyperlink{class_open_chams_1_1_instance}{Open\-Chams\-::\-Instance}
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\item \hyperlink{class_open_chams_1_1_device}{Open\-Chams\-::\-Device}
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\item \hyperlink{class_open_chams_1_1_transistor}{Open\-Chams\-::\-Transistor}
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\item \hyperlink{class_open_chams_1_1_parameters}{Open\-Chams\-::\-Parameters}
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\item \hyperlink{class_open_chams_1_1_net}{Open\-Chams\-::\-Net}
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\end{DoxyItemize}
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\item Sizing
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\begin{DoxyItemize}
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\item \hyperlink{class_open_chams_1_1_sizing}{Open\-Chams\-::\-Sizing}
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\item \hyperlink{class_open_chams_1_1_operator}{Open\-Chams\-::\-Operator}
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\item \hyperlink{class_open_chams_1_1_simul_model}{Open\-Chams\-::\-Simul\-Model}
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\end{DoxyItemize}
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\item Schematic
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\begin{DoxyItemize}
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\item \hyperlink{class_open_chams_1_1_schematic}{Open\-Chams\-::\-Schematic}
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\item \hyperlink{class_open_chams_1_1_port}{Open\-Chams\-::\-Port}
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\item \hyperlink{class_open_chams_1_1_wire}{Open\-Chams\-::\-Wire}
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\item \hyperlink{class_open_chams_1_1_wire_point}{Open\-Chams\-::\-Wire\-Point}
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\item \hyperlink{class_open_chams_1_1_instance_point}{Open\-Chams\-::\-Instance\-Point}
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\item \hyperlink{class_open_chams_1_1_port_point}{Open\-Chams\-::\-Port\-Point}
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\item \hyperlink{class_open_chams_1_1_intermediate_point}{Open\-Chams\-::\-Intermediate\-Point}
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\end{DoxyItemize}
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\item Layout
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\begin{DoxyItemize}
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\item \hyperlink{class_open_chams_1_1_layout}{Open\-Chams\-::\-Layout}
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\item \hyperlink{class_open_chams_1_1_node}{Open\-Chams\-::\-Node}
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\item \hyperlink{class_open_chams_1_1_bloc}{Open\-Chams\-::\-Bloc}
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\item \hyperlink{class_open_chams_1_1_group}{Open\-Chams\-::\-Group}
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\end{DoxyItemize}
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\end{DoxyItemize}\hypertarget{openchams_openChamsParser}{}\subsection{Using the parser}\label{openchams_openChamsParser}
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Simply load an O\-P\-E\-N\-C\-H\-A\-M\-S file using the static function \hyperlink{class_open_chams_1_1_circuit_ad0aa3183bdea59e62f69c295026b7fe7}{Open\-Chams\-::\-Circuit\-::read\-From\-File()} and then get the netlist object (\hyperlink{class_open_chams_1_1_circuit_a4085d6a7b6958ffdd7ab5df7e6d6e53f}{Open\-Chams\-::\-Circuit\-::get\-Netlist()}) or the sizing procedure (\hyperlink{class_open_chams_1_1_circuit_a0ce52bc8747f684ec0123faa8ff97b6d}{Open\-Chams\-::\-Circuit\-::get\-Sizing()}, might be N\-U\-L\-L) or any other useful information (see \hyperlink{class_open_chams_1_1_circuit}{Open\-Chams\-::\-Circuit}).\hypertarget{openchams_openChamsDriver}{}\subsection{Using the driver}\label{openchams_openChamsDriver}
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Using the driver is very simple, user has to create an \hyperlink{class_open_chams_1_1_circuit}{Open\-Chams\-::\-Circuit} object and simply add \hyperlink{class_open_chams_1_1_netlist}{Open\-Chams\-::\-Netlist} (mandatory) and \hyperlink{class_open_chams_1_1_sizing}{Open\-Chams\-::\-Sizing} (optionnal) or \hyperlink{class_open_chams_1_1_schematic}{Open\-Chams\-::\-Schematic} (optionnal) or \hyperlink{class_open_chams_1_1_layout}{Open\-Chams\-::\-Layout} (optinnal) to it. Finally use the \hyperlink{class_open_chams_1_1_circuit_a2eb07935ec946a07edcee2255b781193}{Open\-Chams\-::\-Circuit\-::write\-To\-File()} method to dump the database to file.\hypertarget{openchams_openChamsExamples}{}\section{Examples}\label{openchams_openChamsExamples}
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As said is the global presentation, V\-L\-S\-I S\-A\-P\-D project provides C++ libraries and Python modules for each supported format. In this section we present simple code examples to parse and drive a O\-P\-E\-N\-C\-H\-A\-M\-S file using C++ or Python. The O\-P\-E\-N\-C\-H\-A\-M\-S files considered are the same for all examples\-: {\ttfamily inverter.\-xml} and {\ttfamily buffer.\-xml}
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\begin{DoxyCodeInclude}
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<?xml version=\textcolor{stringliteral}{"1.0"} encoding=\textcolor{stringliteral}{"UTF-8"}?>
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<circuit name=\textcolor{stringliteral}{"inverter"} techno=\textcolor{stringliteral}{"myTech"}>
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<parameters>
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<parameter name=\textcolor{stringliteral}{"temp"} value=\textcolor{stringliteral}{"27.0"}/>
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<parameter name=\textcolor{stringliteral}{"Vdd"} value=\textcolor{stringliteral}{"1.2"}/>
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<parameter name=\textcolor{stringliteral}{"Vss"} value=\textcolor{stringliteral}{"0.0"}/>
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<parameter name=\textcolor{stringliteral}{"L"} value=\textcolor{stringliteral}{"0.10e-6"}/>
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<parameter name=\textcolor{stringliteral}{"Ids"} value=\textcolor{stringliteral}{"30e-6"}/>
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<parameter name=\textcolor{stringliteral}{"Veg"} value=\textcolor{stringliteral}{"0.12"}/>
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<parameterEq name=\textcolor{stringliteral}{"complex"} equation=\textcolor{stringliteral}{"myEq"}/>
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</parameters>
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<netlist>
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<instances>
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<instance name=\textcolor{stringliteral}{"nmos1"} model=\textcolor{stringliteral}{"Transistor"} order=\textcolor{stringliteral}{"1"} mostype=\textcolor{stringliteral}{"NMOS"} sourceBulkConnected=\textcolor{stringliteral}{"True"}>
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<connectors>
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<connector name=\textcolor{stringliteral}{"G"}/>
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<connector name=\textcolor{stringliteral}{"D"}/>
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<connector name=\textcolor{stringliteral}{"S"}/>
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</connectors>
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<transistors>
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<transistor name=\textcolor{stringliteral}{"m1"}>
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<connection gate=\textcolor{stringliteral}{"G"} source=\textcolor{stringliteral}{"S"} drain=\textcolor{stringliteral}{"D"} bulk=\textcolor{stringliteral}{"S"}/>
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</transistor>
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</transistors>
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</instance>
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<instance name=\textcolor{stringliteral}{"pmos1"} model=\textcolor{stringliteral}{"Transistor"} order=\textcolor{stringliteral}{"2"} mostype=\textcolor{stringliteral}{"PMOS"} sourceBulkConnected=\textcolor{stringliteral}{"True"}>
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<connectors>
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<connector name=\textcolor{stringliteral}{"G"}/>
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<connector name=\textcolor{stringliteral}{"D"}/>
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<connector name=\textcolor{stringliteral}{"S"}/>
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</connectors>
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<transistors>
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<transistor name=\textcolor{stringliteral}{"m1"}>
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<connection gate=\textcolor{stringliteral}{"G"} source=\textcolor{stringliteral}{"S"} drain=\textcolor{stringliteral}{"D"} bulk=\textcolor{stringliteral}{"S"}/>
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</transistor>
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</transistors>
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</instance>
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</instances>
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<nets>
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<net name=\textcolor{stringliteral}{"vdd"} type=\textcolor{stringliteral}{"power"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"pmos1"} name=\textcolor{stringliteral}{"S"}/>
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</net>
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<net name=\textcolor{stringliteral}{"vss"} type=\textcolor{stringliteral}{"ground"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"nmos1"} name=\textcolor{stringliteral}{"S"}/>
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</net>
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<net name=\textcolor{stringliteral}{"in"} type=\textcolor{stringliteral}{"logical"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"nmos1"} name=\textcolor{stringliteral}{"G"}/>
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<connector instance=\textcolor{stringliteral}{"pmos1"} name=\textcolor{stringliteral}{"G"}/>
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</net>
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<net name=\textcolor{stringliteral}{"out"} type=\textcolor{stringliteral}{"logical"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"nmos1"} name=\textcolor{stringliteral}{"D"}/>
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<connector instance=\textcolor{stringliteral}{"pmos1"} name=\textcolor{stringliteral}{"D"}/>
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</net>
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</nets>
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</netlist>
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<schematic>
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<instance name=\textcolor{stringliteral}{"nmos1"} x=\textcolor{stringliteral}{"2490"} y=\textcolor{stringliteral}{"2600"} orient=\textcolor{stringliteral}{"ID"}/>
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<instance name=\textcolor{stringliteral}{"pmos1"} x=\textcolor{stringliteral}{"2490"} y=\textcolor{stringliteral}{"2490"} orient=\textcolor{stringliteral}{"ID"}/>
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<net name=\textcolor{stringliteral}{"vdd"}>
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<port type=\textcolor{stringliteral}{"inV"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2525"} y=\textcolor{stringliteral}{"2430"} orient=\textcolor{stringliteral}{"ID"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"pmos1"} plug=\textcolor{stringliteral}{"S"}/>
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<!--point x=\textcolor{stringliteral}{""} y=\textcolor{stringliteral}{""}/-->
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<connector idx=\textcolor{stringliteral}{"0"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"vss"}>
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<port type=\textcolor{stringliteral}{"inV"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2525"} y=\textcolor{stringliteral}{"2740"} orient=\textcolor{stringliteral}{"MY"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"nmos1"} plug=\textcolor{stringliteral}{"S"}/>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"in"}>
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<port type=\textcolor{stringliteral}{"inH"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2415"} y=\textcolor{stringliteral}{"2520"} orient=\textcolor{stringliteral}{"ID"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"pmos1"} plug=\textcolor{stringliteral}{"G"}/>
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<connector name=\textcolor{stringliteral}{"nmos1"} plug=\textcolor{stringliteral}{"G"}/>
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</wire>
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<wire>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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<connector name=\textcolor{stringliteral}{"pmos1"} plug=\textcolor{stringliteral}{"G"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"out"}>
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<port type=\textcolor{stringliteral}{"outH"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2570"} y=\textcolor{stringliteral}{"2590"} orient=\textcolor{stringliteral}{"ID"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"pmos1"} plug=\textcolor{stringliteral}{"D"}/>
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<connector name=\textcolor{stringliteral}{"nmos1"} plug=\textcolor{stringliteral}{"D"}/>
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</wire>
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<wire>
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<connector name=\textcolor{stringliteral}{"nmos1"} plug=\textcolor{stringliteral}{"D"}/>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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</wire>
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</net>
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</schematic>
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<sizing>
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<instance name=\textcolor{stringliteral}{"pmos1"} \textcolor{keyword}{operator}=\textcolor{stringliteral}{"OPVG(Veg)"} simulModel=\textcolor{stringliteral}{"BSIM3V3"}>
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<constraint param=\textcolor{stringliteral}{"Temp"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"temp"}/>
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<constraint param=\textcolor{stringliteral}{"Ids"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Ids"}/>
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<constraint param=\textcolor{stringliteral}{"L"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"L"}/>
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<constraint param=\textcolor{stringliteral}{"Veg"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Veg"}/>
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<constraint param=\textcolor{stringliteral}{"Vd"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Vdd"} factor=\textcolor{stringliteral}{"0.5"}/>
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<constraint param=\textcolor{stringliteral}{"Vs"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Vdd"}/>
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</instance>
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<instance name=\textcolor{stringliteral}{"nmos1"} \textcolor{keyword}{operator}=\textcolor{stringliteral}{"OPW(Vg,Vs)"} simulModel=\textcolor{stringliteral}{"BSIM3V3"}>
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<constraint param=\textcolor{stringliteral}{"Temp"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"temp"}/>
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<constraint param=\textcolor{stringliteral}{"Ids"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Ids"}/>
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<constraint param=\textcolor{stringliteral}{"L"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"L"}/>
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<constraint param=\textcolor{stringliteral}{"Vs"} ref=\textcolor{stringliteral}{"design"} refParam=\textcolor{stringliteral}{"Vdd"}/>
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<constraint param=\textcolor{stringliteral}{"Vg"} ref=\textcolor{stringliteral}{"pmos1"} refParam=\textcolor{stringliteral}{"Vg"}/>
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<constraint param=\textcolor{stringliteral}{"Vd"} ref=\textcolor{stringliteral}{"pmos1"} refParam=\textcolor{stringliteral}{"Vd"}/>
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<constraint param=\textcolor{stringliteral}{"another"} refEquation=\textcolor{stringliteral}{"myEq"} factor=\textcolor{stringliteral}{"-2.5"}/>
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</instance>
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<equations>
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<eq name=\textcolor{stringliteral}{"myEq"} equation=\textcolor{stringliteral}{"A/more+complex*equation"}/>
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</equations>
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</sizing>
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<layout>
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<instance name=\textcolor{stringliteral}{"pmos1"} style=\textcolor{stringliteral}{"Common transistor"}/>
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<instance name=\textcolor{stringliteral}{"nmos1"} style=\textcolor{stringliteral}{"Rotate transistor"}/>
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<hbtree>
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<group name=\textcolor{stringliteral}{"g1"} align=\textcolor{stringliteral}{"vertical"}>
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<bloc name=\textcolor{stringliteral}{"nmos1"}>
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<bloc name=\textcolor{stringliteral}{"pmos1"} position=\textcolor{stringliteral}{"top"}/>
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</bloc>
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</group>
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</hbtree>
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</layout>
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</circuit>
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\end{DoxyCodeInclude}
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\begin{DoxyCodeInclude}
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<?xml version=\textcolor{stringliteral}{"1.0"} encoding=\textcolor{stringliteral}{"UTF-8"}?>
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<circuit name=\textcolor{stringliteral}{"buffer"} techno=\textcolor{stringliteral}{"myTech"}>
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<subCircuitsPaths>
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<path path=\textcolor{stringliteral}{"."}/>
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</subCircuitsPaths>
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<netlist>
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<instances>
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<instance name=\textcolor{stringliteral}{"inv1"} model=\textcolor{stringliteral}{"inverter"}>
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<connectors>
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<connector name=\textcolor{stringliteral}{"vdd"}/>
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<connector name=\textcolor{stringliteral}{"vss"}/>
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<connector name=\textcolor{stringliteral}{"in"} />
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<connector name=\textcolor{stringliteral}{"out"}/>
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</connectors>
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</instance>
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<instance name=\textcolor{stringliteral}{"inv2"} model=\textcolor{stringliteral}{"inverter"}>
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<connectors>
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<connector name=\textcolor{stringliteral}{"vdd"}/>
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<connector name=\textcolor{stringliteral}{"vss"}/>
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<connector name=\textcolor{stringliteral}{"in"} />
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<connector name=\textcolor{stringliteral}{"out"}/>
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</connectors>
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</instance>
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</instances>
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<nets>
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<net name=\textcolor{stringliteral}{"vdd"} type=\textcolor{stringliteral}{"power"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"inv1"} name=\textcolor{stringliteral}{"vdd"}/>
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<connector instance=\textcolor{stringliteral}{"inv2"} name=\textcolor{stringliteral}{"vdd"}/>
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</net>
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<net name=\textcolor{stringliteral}{"vss"} type=\textcolor{stringliteral}{"ground"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"inv1"} name=\textcolor{stringliteral}{"vss"}/>
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<connector instance=\textcolor{stringliteral}{"inv2"} name=\textcolor{stringliteral}{"vss"}/>
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</net>
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<net name=\textcolor{stringliteral}{"in"} type=\textcolor{stringliteral}{"logical"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"inv1"} name=\textcolor{stringliteral}{"in"}/>
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</net>
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<net name=\textcolor{stringliteral}{"out"} type=\textcolor{stringliteral}{"logical"} isExternal=\textcolor{stringliteral}{"True"}>
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<connector instance=\textcolor{stringliteral}{"inv2"} name=\textcolor{stringliteral}{"out"}/>
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</net>
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<net name=\textcolor{stringliteral}{"internal"} type=\textcolor{stringliteral}{"logical"} isExternal=\textcolor{stringliteral}{"False"}>
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<connector instance=\textcolor{stringliteral}{"inv1"} name=\textcolor{stringliteral}{"out"}/>
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<connector instance=\textcolor{stringliteral}{"inv2"} name=\textcolor{stringliteral}{"in"}/>
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</net>
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</nets>
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</netlist>
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<schematic>
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<instance name=\textcolor{stringliteral}{"inv1"} x=\textcolor{stringliteral}{"2490"} y=\textcolor{stringliteral}{"2600"} orient=\textcolor{stringliteral}{"ID"}/>
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<instance name=\textcolor{stringliteral}{"inv2"} x=\textcolor{stringliteral}{"2490"} y=\textcolor{stringliteral}{"2300"} orient=\textcolor{stringliteral}{"ID"}/>
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<net name=\textcolor{stringliteral}{"in"}>
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<port type=\textcolor{stringliteral}{"inV"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2415"} y=\textcolor{stringliteral}{"2700"} orient=\textcolor{stringliteral}{"MY"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"inv1"} plug=\textcolor{stringliteral}{"in"}/>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"internal"}>
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<wire>
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<connector name=\textcolor{stringliteral}{"inv1"} plug=\textcolor{stringliteral}{"out"}/>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"in"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"out"}>
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<port type=\textcolor{stringliteral}{"outV"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2415"} y=\textcolor{stringliteral}{"2200"} orient=\textcolor{stringliteral}{"MY"}/>
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<wire>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"out"}/>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"vdd"}>
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<port type=\textcolor{stringliteral}{"inH"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2200"} y=\textcolor{stringliteral}{"2500"} orient=\textcolor{stringliteral}{"ID"}/>
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<wire>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"vdd"}/>
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</wire>
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<wire>
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<connector name=\textcolor{stringliteral}{"inv1"} plug=\textcolor{stringliteral}{"vdd"}/>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"vdd"}/>
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</wire>
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</net>
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<net name=\textcolor{stringliteral}{"vss"}>
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<port type=\textcolor{stringliteral}{"inH"} idx=\textcolor{stringliteral}{"0"} x=\textcolor{stringliteral}{"2700"} y=\textcolor{stringliteral}{"2500"} orient=\textcolor{stringliteral}{"MX"}/>
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<wire>
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<connector idx=\textcolor{stringliteral}{"0"}/>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"vss"}/>
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</wire>
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<wire>
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<connector name=\textcolor{stringliteral}{"inv1"} plug=\textcolor{stringliteral}{"vss"}/>
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<connector name=\textcolor{stringliteral}{"inv2"} plug=\textcolor{stringliteral}{"vss"}/>
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</wire>
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</net>
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</schematic>
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</circuit>
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\end{DoxyCodeInclude}
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All source codes are available in the {\ttfamily examples} directory.\hypertarget{openchams_openChamsC}{}\subsection{C++}\label{openchams_openChamsC}
|
||
\hypertarget{openchams_openChamsParseC}{}\subsubsection{Parser}\label{openchams_openChamsParseC}
|
||
The following code ({\ttfamily parse\-Open\-Chams.\-cpp}) is an example of how to parse a O\-P\-E\-N\-C\-H\-A\-M\-S file using C++ library.
|
||
\begin{DoxyCodeInclude}
|
||
\textcolor{preprocessor}{#include <iostream>}
|
||
\textcolor{preprocessor}{#include <string>}
|
||
\textcolor{preprocessor}{#include <map>}
|
||
\textcolor{preprocessor}{#include <vector>}
|
||
\textcolor{keyword}{using namespace }std;
|
||
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Circuit.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Name.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Parameters.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Netlist.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Instance.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Device.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Net.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Transistor.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Schematic.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Sizing.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Operator.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Layout.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Node.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Port.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Wire.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/OpenChamsException.h"}
|
||
|
||
\textcolor{keywordtype}{void} printHBTree(\hyperlink{class_open_chams_1_1_node}{OpenChams::Node}* node, \textcolor{keywordtype}{unsigned} indent) \{
|
||
\textcolor{keywordflow}{if} (!node) \textcolor{keywordflow}{return}; \textcolor{comment}{// since we pass nnode->getRight and node-getTop without checking for NULL}
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{unsigned} i = 0 ; i < indent ; i++) \{
|
||
cerr << \textcolor{stringliteral}{" |"};
|
||
\}
|
||
\textcolor{keywordtype}{string} pos = \textcolor{stringliteral}{""};
|
||
\textcolor{keywordflow}{switch}(node->\hyperlink{class_open_chams_1_1_node_a2843ffc4a8a476bc6d96d9a155d3071e}{getPosition}()) \{
|
||
\textcolor{keywordflow}{case} OpenChams::Node::TOP:
|
||
pos = \textcolor{stringliteral}{"top"};
|
||
\textcolor{keywordflow}{break};
|
||
\textcolor{keywordflow}{case} OpenChams::Node::RIGHT:
|
||
pos = \textcolor{stringliteral}{"right"};
|
||
\textcolor{keywordflow}{break};
|
||
\textcolor{keywordflow}{default}:
|
||
\textcolor{keywordflow}{break};
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}* bloc = \textcolor{keyword}{dynamic\_cast<}\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}*\textcolor{keyword}{>}(node);
|
||
\textcolor{keywordflow}{if} (bloc) \{
|
||
cerr << \textcolor{stringliteral}{" bloc: "} << bloc->\hyperlink{class_open_chams_1_1_node_aef436e6e20d1dbf2eb78b089ca9d0794}{getName}().getString() << \textcolor{stringliteral}{" - "} << pos << endl;
|
||
printHBTree(bloc->\hyperlink{class_open_chams_1_1_node_af59967a8c2d5a04ca0a58e2ef29bead1}{getTop}() , indent+1);
|
||
printHBTree(bloc->\hyperlink{class_open_chams_1_1_node_a9533ddcf078ddfc2a4e9bd9ffafa51cb}{getRight}(), indent+1);
|
||
\textcolor{keywordflow}{return};
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}* group = \textcolor{keyword}{dynamic\_cast<}\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}*\textcolor{keyword}{>}(node);
|
||
\textcolor{keywordflow}{if} (group) \{
|
||
\textcolor{keywordtype}{string} align = \textcolor{stringliteral}{"none"};
|
||
\textcolor{keywordflow}{switch}(group->\hyperlink{class_open_chams_1_1_group_a7cff0c4a6957f23fb1ea4598f4b8a0b8}{getAlign}()) \{
|
||
\textcolor{keywordflow}{case} OpenChams::Group::VERTICAL:
|
||
align = \textcolor{stringliteral}{"vertical"};
|
||
\textcolor{keywordflow}{break};
|
||
\textcolor{keywordflow}{case} OpenChams::Group::HORIZONTAL:
|
||
align = \textcolor{stringliteral}{"horizontal"};
|
||
\textcolor{keywordflow}{break};
|
||
\textcolor{keywordflow}{default}:
|
||
\textcolor{keywordflow}{break};
|
||
\}
|
||
cerr << \textcolor{stringliteral}{" group: "} << group->\hyperlink{class_open_chams_1_1_node_aef436e6e20d1dbf2eb78b089ca9d0794}{getName}().getString() << \textcolor{stringliteral}{" - "} << pos << \textcolor{stringliteral}{" - align: "} << align
|
||
<< \textcolor{stringliteral}{" - isolated: "} << group->\hyperlink{class_open_chams_1_1_group_ab5ae4a4550c418c974ff6e59967eeec2}{isIsolated}() << \textcolor{stringliteral}{" - paired: "} << group->
|
||
\hyperlink{class_open_chams_1_1_group_aee0abf07a6e9d41f511c648e6eaecea3}{isPaired}() << endl;
|
||
printHBTree(group->getRootNode(), indent+1);
|
||
printHBTree(group->\hyperlink{class_open_chams_1_1_node_af59967a8c2d5a04ca0a58e2ef29bead1}{getTop}() , indent+1);
|
||
printHBTree(group->\hyperlink{class_open_chams_1_1_node_a9533ddcf078ddfc2a4e9bd9ffafa51cb}{getRight}() , indent+1);
|
||
\textcolor{keywordflow}{return};
|
||
\}
|
||
cerr << \textcolor{stringliteral}{"[ERROR] printHBTree: node is nor a bloc nor a group !"} << endl;
|
||
\textcolor{keywordflow}{return};
|
||
\}
|
||
|
||
\textcolor{keywordtype}{int} main(\textcolor{keywordtype}{int} argc, \textcolor{keywordtype}{char} * argv[]) \{
|
||
\textcolor{keywordtype}{string} file = \textcolor{stringliteral}{""};
|
||
\textcolor{keywordflow}{if} (argc == 1)
|
||
file = \textcolor{stringliteral}{"./inverter.xml"};
|
||
\textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (argc == 2)
|
||
file = argv[1];
|
||
\textcolor{keywordflow}{else} \{
|
||
cerr << \textcolor{stringliteral}{"Usage: openChamsParser [filename]"} << endl;
|
||
exit(1);
|
||
\}
|
||
|
||
\hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}* circuit = NULL;
|
||
\textcolor{keywordflow}{try} \{
|
||
circuit = \hyperlink{class_open_chams_1_1_circuit_ad0aa3183bdea59e62f69c295026b7fe7}{OpenChams::Circuit::readFromFile}(file);
|
||
\} \textcolor{keywordflow}{catch} (\hyperlink{class_open_chams_1_1_open_chams_exception}{OpenChams::OpenChamsException}& e) \{
|
||
cerr << e.what() << endl;
|
||
exit(48);
|
||
\}
|
||
|
||
cerr << circuit->\hyperlink{class_open_chams_1_1_circuit_a2858c0c4e8b5108f041237cf5a802029}{getName}().getString() << endl;
|
||
cerr << \textcolor{stringliteral}{" + parameters"} << endl;
|
||
\hyperlink{class_open_chams_1_1_parameters}{OpenChams::Parameters} params = circuit->\hyperlink{class_open_chams_1_1_circuit_a2e51ad4344607fc279c5c8cda4edae02}{getParameters}();
|
||
\textcolor{keywordflow}{if} (!params.\hyperlink{class_open_chams_1_1_parameters_af337ffd75e4f019ce15302c60715d84b}{isEmpty}()) \{
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, string>::const\_iterator it = params.\hyperlink{class_open_chams_1_1_parameters_a0f890d16c3b2a0bcbdf060854ea07877}{getValues}().begin() ; it !=
|
||
params.\hyperlink{class_open_chams_1_1_parameters_a0f890d16c3b2a0bcbdf060854ea07877}{getValues}().end() ; ++it) \{
|
||
cerr << \textcolor{stringliteral}{" | | "} << ((*it).first).getString() << \textcolor{stringliteral}{" : "} << (*it).second << endl;
|
||
\}
|
||
\}
|
||
cerr << \textcolor{stringliteral}{" + netlist"} << endl;
|
||
cerr << \textcolor{stringliteral}{" | + instances"} << endl;
|
||
\hyperlink{class_open_chams_1_1_netlist}{OpenChams::Netlist}* netlist = circuit->\hyperlink{class_open_chams_1_1_circuit_a4085d6a7b6958ffdd7ab5df7e6d6e53f}{getNetlist}();
|
||
\textcolor{keywordflow}{if} (netlist && !netlist->\hyperlink{class_open_chams_1_1_netlist_adab62a25face462baec9a7fffb2b6158}{hasNoInstances}()) \{
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\hyperlink{class_open_chams_1_1_netlist_a8e6e58ffab876152a740092520c35d73}{getInstances}().size() ; i++) \{
|
||
\hyperlink{class_open_chams_1_1_instance}{OpenChams::Instance}* inst = netlist->\hyperlink{class_open_chams_1_1_netlist_a8e6e58ffab876152a740092520c35d73}{getInstances}()[i];
|
||
\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}* dev = NULL;
|
||
\textcolor{keywordflow}{if} (dynamic\_cast<OpenChams::Device*>(inst)) \{
|
||
dev = \textcolor{keyword}{static\_cast<}\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}*\textcolor{keyword}{>}(inst);
|
||
cerr << \textcolor{stringliteral}{" | | + "} << dev->getName().getString() << \textcolor{stringliteral}{" : "} << dev->getModel().getString() << \textcolor{stringliteral}{
|
||
" - "} << dev->getOrder() << \textcolor{stringliteral}{" - "} << dev->\hyperlink{class_open_chams_1_1_device_a831ce553c23908f447a5be332ecd5946}{getMosType}().getString() << \textcolor{stringliteral}{" - "} << (dev->
|
||
\hyperlink{class_open_chams_1_1_device_a29ed1982e1a8b3a634df8d0c70039669}{isSourceBulkConnected}()?\textcolor{stringliteral}{"true"}:\textcolor{stringliteral}{"false"}) << endl;
|
||
\} \textcolor{keywordflow}{else} \{
|
||
cerr << \textcolor{stringliteral}{" | | + "} << inst->getName().getString() << \textcolor{stringliteral}{" : "} << inst->getModel().getString() <
|
||
< \textcolor{stringliteral}{" - "} << inst->getOrder() << endl;
|
||
\}
|
||
cerr << \textcolor{stringliteral}{" | | | + connectors"} << endl;
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, OpenChams::Net*>::const\_iterator cit = inst->
|
||
\hyperlink{class_open_chams_1_1_instance_a745fe0a50eb770ce3bea36ef0e62c8ca}{getConnectors}().begin() ; cit != inst->\hyperlink{class_open_chams_1_1_instance_a745fe0a50eb770ce3bea36ef0e62c8ca}{getConnectors}().end() ; ++cit) \{
|
||
\textcolor{keywordflow}{if} ((*cit).second)
|
||
cerr << \textcolor{stringliteral}{" | | | | "} << ((*cit).first).getString() << \textcolor{stringliteral}{" : "} << ((*cit).second)->getName(
|
||
).getString() << endl;
|
||
\textcolor{keywordflow}{else}
|
||
cerr << \textcolor{stringliteral}{" | | | | "} << ((*cit).first).getString() << endl; \textcolor{comment}{// no net connected !}
|
||
\}
|
||
\textcolor{keywordflow}{if} (dev) \{
|
||
cerr << \textcolor{stringliteral}{" | | | + transistors"} << endl;
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < dev->\hyperlink{class_open_chams_1_1_device_a4033525cab6387eb057f71f5feed9802}{getTransistors}().size() ; j++) \{
|
||
\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}* tr = dev->
|
||
\hyperlink{class_open_chams_1_1_device_a4033525cab6387eb057f71f5feed9802}{getTransistors}()[j];
|
||
cerr << \textcolor{stringliteral}{" | | | | name: "} << tr->\hyperlink{class_open_chams_1_1_transistor_a2858c0c4e8b5108f041237cf5a802029}{getName}().getString() << \textcolor{stringliteral}{" - gate: "} << tr->
|
||
\hyperlink{class_open_chams_1_1_transistor_a99f1449aa735ff6cb4927b4f6aa34d9d}{getGate}().getString() << \textcolor{stringliteral}{" - source: "} << tr->\hyperlink{class_open_chams_1_1_transistor_aee4d52a0b13e6db247c1a6c051aede25}{getSource}().getString() << \textcolor{stringliteral}{" - drain: "} << tr
|
||
->\hyperlink{class_open_chams_1_1_transistor_a62ea0998b3a61310a8331873f5bcce58}{getDrain}().getString() << \textcolor{stringliteral}{" - bulk: "} << tr->\hyperlink{class_open_chams_1_1_transistor_a27ba43f825f9243556ec65d306a2b1a7}{getBulk}().getString() << endl;
|
||
\}
|
||
\}
|
||
\}
|
||
\}
|
||
cerr << \textcolor{stringliteral}{" | + nets"} << endl;
|
||
\textcolor{keywordtype}{bool} schematicNet = \textcolor{keyword}{false}; \textcolor{comment}{// define wether net sections are needed in schematic section}
|
||
\textcolor{keywordflow}{if} (!netlist->\hyperlink{class_open_chams_1_1_netlist_a36089e1b3a3f2d3f7c9dcc8e3c3bd6d8}{hasNoNets}()) \{
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}().size() ; i++) \{
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* net = netlist->\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}()[i];
|
||
cerr << \textcolor{stringliteral}{" | | + "} << net->\hyperlink{class_open_chams_1_1_net_aef436e6e20d1dbf2eb78b089ca9d0794}{getName}().getString() << \textcolor{stringliteral}{" : "} << net->
|
||
\hyperlink{class_open_chams_1_1_net_a7a88ff26f0ba9cfbfa5059c565d1e30b}{getType}().getString() << \textcolor{stringliteral}{" - "} << (net->\hyperlink{class_open_chams_1_1_net_ab2570574db49633f58f7b64099d6852c}{isExternal}()?\textcolor{stringliteral}{"true"}:\textcolor{stringliteral}{"false"}) << endl;
|
||
cerr << \textcolor{stringliteral}{" | | | + connections"} << endl;
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\hyperlink{class_open_chams_1_1_net_a87e7c71b25171dd479af0488865c8179}{getConnections}().size() ; j++) \{
|
||
\hyperlink{class_open_chams_1_1_net_1_1_connection}{OpenChams::Net::Connection}* connect = net->
|
||
\hyperlink{class_open_chams_1_1_net_a87e7c71b25171dd479af0488865c8179}{getConnections}()[j];
|
||
cerr << \textcolor{stringliteral}{" | | | | "} << connect->\hyperlink{class_open_chams_1_1_net_1_1_connection_a44e43ff95d18d91abb9449a09e3c9d1f}{getInstanceName}().getString() << \textcolor{stringliteral}{"."} <<
|
||
connect->\hyperlink{class_open_chams_1_1_net_1_1_connection_a42f70d94ed3768e0342ae2bcb09ac0ed}{getConnectorName}().getString() << endl;
|
||
\}
|
||
\textcolor{keywordflow}{if} (!net->\hyperlink{class_open_chams_1_1_net_a3eef7a6d1e945441f197f0918ab8895e}{hasNoPorts}() || !net->\hyperlink{class_open_chams_1_1_net_ac9470e72b26d4cddef3d13e69057ee54}{hasNoWires}())
|
||
schematicNet = \textcolor{keyword}{true};
|
||
\}
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_schematic}{OpenChams::Schematic}* schematic = circuit->\hyperlink{class_open_chams_1_1_circuit_af6f967a5685ac92fe760f4eb95c8c51f}{getSchematic}();
|
||
\textcolor{keywordflow}{if} (schematic && !schematic->\hyperlink{class_open_chams_1_1_schematic_adab62a25face462baec9a7fffb2b6158}{hasNoInstances}()) \{
|
||
cerr << \textcolor{stringliteral}{" + schematic"} << endl;
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, OpenChams::Schematic::Infos*>::const\_iterator sit = schematic->
|
||
\hyperlink{class_open_chams_1_1_schematic_afa015b02922d82de9c44e8ffe8dc5d56}{getInstances}().begin() ; sit != schematic->\hyperlink{class_open_chams_1_1_schematic_afa015b02922d82de9c44e8ffe8dc5d56}{getInstances}().end() ; ++sit) \{
|
||
\hyperlink{class_open_chams_1_1_schematic_1_1_infos}{OpenChams::Schematic::Infos}* inf = (*sit).second;
|
||
cerr << \textcolor{stringliteral}{" | + instance: name: "} << ((*sit).first).getString() << \textcolor{stringliteral}{" - x: "} << inf->
|
||
\hyperlink{class_open_chams_1_1_schematic_1_1_infos_a2b69e4312b7814c6efce42f851893409}{getX}() << \textcolor{stringliteral}{" - y: "} << inf->\hyperlink{class_open_chams_1_1_schematic_1_1_infos_a15f19cf52955c8c3406831b288681358}{getY}() << \textcolor{stringliteral}{" - orientation: "} << inf->
|
||
\hyperlink{class_open_chams_1_1_schematic_1_1_infos_ac7e0f89be2baffb526b2dca46da7aa47}{getOrientation}().getString() << endl;
|
||
\}
|
||
\textcolor{keywordflow}{if} (schematicNet) \{
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} i = 0 ; i < netlist->\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}().size() ; i++) \{
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* net = netlist->\hyperlink{class_open_chams_1_1_netlist_abf36db82efb99a8ec8ae4b454be00019}{getNets}()[i];
|
||
cerr << \textcolor{stringliteral}{" | + net name: "} << net->\hyperlink{class_open_chams_1_1_net_aef436e6e20d1dbf2eb78b089ca9d0794}{getName}().getString() << endl;
|
||
\textcolor{keywordflow}{if} (!net->\hyperlink{class_open_chams_1_1_net_a3eef7a6d1e945441f197f0918ab8895e}{hasNoPorts}()) \{
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\hyperlink{class_open_chams_1_1_net_ae9d241ec6dd833b6d7813e14ff2d9eca}{getPorts}().size() ; j++) \{
|
||
\hyperlink{class_open_chams_1_1_port}{OpenChams::Port}* port = net->\hyperlink{class_open_chams_1_1_net_ae9d241ec6dd833b6d7813e14ff2d9eca}{getPorts}()[j];
|
||
cerr << \textcolor{stringliteral}{" | | + port type: "} << port->\hyperlink{class_open_chams_1_1_port_a03950ba8678003d3a246bbd1d03cfbfb}{getType}().getString() << \textcolor{stringliteral}{" - idx: "} <
|
||
< port->\hyperlink{class_open_chams_1_1_port_affe6668af1b3e04a80ff75e55f8024ef}{getIndex}() << \textcolor{stringliteral}{" - x: "} << port->\hyperlink{class_open_chams_1_1_port_af71e522ec6aa935c2618819b54f20e02}{getX}() << \textcolor{stringliteral}{" - y: "} << port->
|
||
\hyperlink{class_open_chams_1_1_port_acd84440598b1da2a23c326ce371db4e4}{getY}() << \textcolor{stringliteral}{" - orientation: "} << port->\hyperlink{class_open_chams_1_1_port_acbe891eaa3be07cacb7385362ab98ecc}{getOrientation}().getString() << endl;
|
||
\}
|
||
\}
|
||
\textcolor{keywordflow}{if} (!net->\hyperlink{class_open_chams_1_1_net_ac9470e72b26d4cddef3d13e69057ee54}{hasNoWires}()) \{
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} j = 0 ; j < net->\hyperlink{class_open_chams_1_1_net_a2f8bcf7cad7711850efeca408f146b8a}{getWires}().size() ; j++) \{
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wire = net->\hyperlink{class_open_chams_1_1_net_a2f8bcf7cad7711850efeca408f146b8a}{getWires}()[j];
|
||
cerr << \textcolor{stringliteral}{" | | + wire "};
|
||
\hyperlink{class_open_chams_1_1_wire_point}{OpenChams::WirePoint}* start = wire->
|
||
\hyperlink{class_open_chams_1_1_wire_ad68ddfcb6d4cbbe3c06d03fb4350dcdb}{getStartPoint}();
|
||
\textcolor{keywordflow}{if} (dynamic\_cast<OpenChams::InstancePoint*>(start)) \{
|
||
\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}* iP = \textcolor{keyword}{static\_cast<}
|
||
\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}*\textcolor{keyword}{>}(start);
|
||
cerr << \textcolor{stringliteral}{"<"} << iP->\hyperlink{class_open_chams_1_1_instance_point_a2858c0c4e8b5108f041237cf5a802029}{getName}().getString() << \textcolor{stringliteral}{","} << iP->
|
||
\hyperlink{class_open_chams_1_1_instance_point_a646d464666fc56ab2e04a6b87fdd3279}{getPlug}().getString() << \textcolor{stringliteral}{"> "};
|
||
\} \textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (dynamic\_cast<OpenChams::PortPoint*>(start)) \{
|
||
\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}* pP = \textcolor{keyword}{static\_cast<}
|
||
\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}*\textcolor{keyword}{>}(start);
|
||
cerr << \textcolor{stringliteral}{"<"} << pP->\hyperlink{class_open_chams_1_1_port_point_ab4018980dcd1fed5208e7a72846cd815}{getIndex}() << \textcolor{stringliteral}{"> "};
|
||
\}
|
||
\textcolor{keywordflow}{for} (\textcolor{keywordtype}{size\_t} k = 0 ; k < wire->\hyperlink{class_open_chams_1_1_wire_aac2840e22e03db0ff2c0fe0f83c56fdd}{getIntermediatePoints}().size() ;
|
||
k++) \{
|
||
\hyperlink{class_open_chams_1_1_intermediate_point}{OpenChams::IntermediatePoint}* iP = wire->
|
||
\hyperlink{class_open_chams_1_1_wire_aac2840e22e03db0ff2c0fe0f83c56fdd}{getIntermediatePoints}()[k];
|
||
cerr << \textcolor{stringliteral}{"<"} << iP->\hyperlink{class_open_chams_1_1_intermediate_point_a2b69e4312b7814c6efce42f851893409}{getX}() << \textcolor{stringliteral}{","} << iP->\hyperlink{class_open_chams_1_1_intermediate_point_a15f19cf52955c8c3406831b288681358}{getY}() << \textcolor{stringliteral}{"> "};
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_wire_point}{OpenChams::WirePoint}* end = wire->
|
||
\hyperlink{class_open_chams_1_1_wire_ab1c91025a4117cede119f53d9eb8093b}{getEndPoint}();
|
||
\textcolor{keywordflow}{if} (dynamic\_cast<OpenChams::InstancePoint*>(end)) \{
|
||
\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}* iP = \textcolor{keyword}{static\_cast<}
|
||
\hyperlink{class_open_chams_1_1_instance_point}{OpenChams::InstancePoint}*\textcolor{keyword}{>}(end);
|
||
cerr << \textcolor{stringliteral}{"<"} << iP->\hyperlink{class_open_chams_1_1_instance_point_a2858c0c4e8b5108f041237cf5a802029}{getName}().getString() << \textcolor{stringliteral}{","} << iP->
|
||
\hyperlink{class_open_chams_1_1_instance_point_a646d464666fc56ab2e04a6b87fdd3279}{getPlug}().getString() << \textcolor{stringliteral}{"> "};
|
||
\} \textcolor{keywordflow}{else} \textcolor{keywordflow}{if} (dynamic\_cast<OpenChams::PortPoint*>(end)) \{
|
||
\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}* pP = \textcolor{keyword}{static\_cast<}
|
||
\hyperlink{class_open_chams_1_1_port_point}{OpenChams::PortPoint}*\textcolor{keyword}{>}(end);
|
||
cerr << \textcolor{stringliteral}{"<"} << pP->\hyperlink{class_open_chams_1_1_port_point_ab4018980dcd1fed5208e7a72846cd815}{getIndex}() << \textcolor{stringliteral}{"> "};
|
||
\}
|
||
cerr << endl;
|
||
\}
|
||
\}
|
||
|
||
\}
|
||
\}
|
||
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_sizing}{OpenChams::Sizing}* sizing = circuit->\hyperlink{class_open_chams_1_1_circuit_a0ce52bc8747f684ec0123faa8ff97b6d}{getSizing}();
|
||
\textcolor{keywordflow}{if} (sizing) \{
|
||
cerr << \textcolor{stringliteral}{" + sizing"} << endl;
|
||
\textcolor{keywordflow}{if} (!sizing->\hyperlink{class_open_chams_1_1_sizing_ac8a299add4fd32ff8bf99c889f4a79a6}{hasNoOperators}()) \{
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, OpenChams::Operator*>::const\_iterator oit = sizing->
|
||
\hyperlink{class_open_chams_1_1_sizing_ad35c9083b30dac45186f4f0eb49b435d}{getOperators}().begin() ; oit != sizing->\hyperlink{class_open_chams_1_1_sizing_ad35c9083b30dac45186f4f0eb49b435d}{getOperators}().end() ; ++oit) \{
|
||
\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}* op = (*oit).second;
|
||
cerr << \textcolor{stringliteral}{" | + instance name: "} << ((*oit).first).getString() << \textcolor{stringliteral}{" - operator: "} << op->
|
||
\hyperlink{class_open_chams_1_1_operator_a2858c0c4e8b5108f041237cf5a802029}{getName}().getString() << \textcolor{stringliteral}{" - simulModel: "} << op->\hyperlink{class_open_chams_1_1_operator_aa189a1b119b44a8877c478e2d2357a89}{getSimulModel}().getString() << endl;
|
||
\textcolor{keywordflow}{if} (!op->\hyperlink{class_open_chams_1_1_operator_a9ac68ad3e43b1649a8582c8685f4886d}{hasNoConstraints}()) \{
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, OpenChams::Operator::Constraint*>::const\_iterator cit = op->
|
||
\hyperlink{class_open_chams_1_1_operator_a0002889b395185948d7c71b261343620}{getConstraints}().begin() ; cit != op->\hyperlink{class_open_chams_1_1_operator_a0002889b395185948d7c71b261343620}{getConstraints}().end() ; ++cit) \{
|
||
\hyperlink{class_open_chams_1_1_operator_1_1_constraint}{OpenChams::Operator::Constraint}* cstr = (*cit).
|
||
second;
|
||
cerr << \textcolor{stringliteral}{" | | + param: "} << ((*cit).first).getString() << \textcolor{stringliteral}{" - ref: "} << cstr->
|
||
\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a07cf74adaf661f0aaaa1818d24c2243d}{getRef}().getString() << \textcolor{stringliteral}{" - refParam: "} << cstr->\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a621539b1a4f31053649031c8034b0bd3}{getRefParam}().getString() << \textcolor{stringliteral}{" - factor:
|
||
"} << cstr->\hyperlink{class_open_chams_1_1_operator_1_1_constraint_a973fc85365f2d3f07007d88a90d7ab1d}{getFactor}() << endl;
|
||
\}
|
||
\}
|
||
\}
|
||
\}
|
||
\textcolor{comment}{// To update to the new equations.}
|
||
\textcolor{comment}{// if (!sizing->hasNoEquations()) \{}
|
||
\textcolor{comment}{// cerr << " | + equations" << endl;}
|
||
\textcolor{comment}{// for (map<OpenChams::Name, string>::const\_iterator eit = sizing->getEquations().begin() ; eit
|
||
!= sizing->getEquations().end() ; ++eit) \{}
|
||
\textcolor{comment}{// cerr << " | | " << ((*eit).first).getString() << " : " << (*eit).second << endl;}
|
||
\textcolor{comment}{// \}}
|
||
\textcolor{comment}{// \}}
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_layout}{OpenChams::Layout}* layout = circuit->\hyperlink{class_open_chams_1_1_circuit_a403a908943f9a3e820fd25a86d00531d}{getLayout}();
|
||
\textcolor{keywordflow}{if} (layout) \{
|
||
\textcolor{keywordflow}{if} (!layout->\hyperlink{class_open_chams_1_1_layout_af27a31f10fcf22daa64f35c9c6bd2cda}{hasNoInstance}()) \{
|
||
cerr << \textcolor{stringliteral}{" + layout"} << endl;
|
||
\textcolor{keywordflow}{for} (map<OpenChams::Name, OpenChams::Name>::const\_iterator lit = layout->
|
||
\hyperlink{class_open_chams_1_1_layout_ab0550a9050b7e788b2a18452c9df21f7}{getInstances}().begin() ; lit != layout->\hyperlink{class_open_chams_1_1_layout_ab0550a9050b7e788b2a18452c9df21f7}{getInstances}().end() ; ++lit) \{
|
||
cerr << \textcolor{stringliteral}{" | | instance name: "} << ((*lit).first).getString() << \textcolor{stringliteral}{" - style: "} << ((*lit).second
|
||
).getString() << endl;
|
||
\}
|
||
\}
|
||
\hyperlink{class_open_chams_1_1_node}{OpenChams::Node}* root = layout->\hyperlink{class_open_chams_1_1_layout_a13df4992219ef28a7dc014e9f5f0566a}{getHBTreeRoot}();
|
||
\textcolor{keywordflow}{if} (root) \{
|
||
cerr << \textcolor{stringliteral}{" | + hbtree"} << endl;
|
||
printHBTree(root, 2);
|
||
\}
|
||
\}
|
||
|
||
|
||
\textcolor{keywordflow}{return} 0;
|
||
\}
|
||
|
||
\end{DoxyCodeInclude}
|
||
\hypertarget{openchams_openChamsDriveC}{}\subsubsection{Driver}\label{openchams_openChamsDriveC}
|
||
This C++ code ({\ttfamily drive\-Open\-Chams.\-cpp}) generates an inverter.\-xml file equivalent to the included one.
|
||
\begin{DoxyCodeInclude}
|
||
\textcolor{preprocessor}{#include <string>}
|
||
\textcolor{keyword}{using namespace }std;
|
||
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Circuit.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Netlist.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Instance.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Device.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Transistor.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Net.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Schematic.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Sizing.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Operator.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Layout.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Node.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Port.h"}
|
||
\textcolor{preprocessor}{#include "vlsisapd/openChams/Wire.h"}
|
||
|
||
\textcolor{keywordtype}{int} main(\textcolor{keywordtype}{int} argc, \textcolor{keywordtype}{char} * argv[]) \{
|
||
\hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}* circuit = \textcolor{keyword}{new} \hyperlink{class_open_chams_1_1_circuit}{OpenChams::Circuit}(
|
||
OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"myTech"}));
|
||
\textcolor{comment}{// value parameters}
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"temp"}), \textcolor{stringliteral}{"27.0"} );
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) , \textcolor{stringliteral}{"1.2"} );
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Vss"}) , \textcolor{stringliteral}{"0.0"} );
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"L"}) , \textcolor{stringliteral}{"0.1e-6"});
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , \textcolor{stringliteral}{"30e-6"} );
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"Veg"}) , \textcolor{stringliteral}{"0.12"} );
|
||
\textcolor{comment}{// equation parameters}
|
||
circuit->addParameter(OpenChams::Name(\textcolor{stringliteral}{"complex"}), \textcolor{stringliteral}{"myEq"});
|
||
|
||
\textcolor{comment}{// netlist}
|
||
\hyperlink{class_open_chams_1_1_netlist}{OpenChams::Netlist}* netlist = circuit->\hyperlink{class_open_chams_1_1_circuit_a3f11671c7ea7b4e2cc3487bd7954b667}{createNetlist}();
|
||
\textcolor{comment}{// instances}
|
||
\textcolor{comment}{// nmos1}
|
||
\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}* inst\_nmos1 = netlist->\hyperlink{class_open_chams_1_1_netlist_a8e1798a2516c32fbab629ce8d60d4b1d}{addDevice}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}),
|
||
OpenChams::Name(\textcolor{stringliteral}{"Transistor"}), 1, OpenChams::Name(\textcolor{stringliteral}{"NMOS"}), \textcolor{keyword}{true});
|
||
inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
inst\_nmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}* tr\_nmos1 = inst\_nmos1->
|
||
\hyperlink{class_open_chams_1_1_device_ad45d34f8765dd113a5b12289efe66c07}{addTransistor}(OpenChams::Name(\textcolor{stringliteral}{"m1"}));
|
||
tr\_nmos1->\hyperlink{class_open_chams_1_1_transistor_a705b53a51f0e265533b228f6e8beaf50}{setGate} (OpenChams::Name(\textcolor{stringliteral}{"G"})); \textcolor{comment}{// the name of the connector of inst\_nmos1}
|
||
tr\_nmos1->\hyperlink{class_open_chams_1_1_transistor_abc4a5d86e639ea13e27551722e2f9c17}{setSource}(OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
tr\_nmos1->\hyperlink{class_open_chams_1_1_transistor_a72ff8491040e3fdc1c8bd62b2392ab82}{setDrain} (OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
tr\_nmos1->\hyperlink{class_open_chams_1_1_transistor_a1484abe63e3f8ffbc2911c5230fa7091}{setBulk} (OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
\textcolor{comment}{// pmos1}
|
||
\hyperlink{class_open_chams_1_1_device}{OpenChams::Device}* inst\_pmos1 = netlist->\hyperlink{class_open_chams_1_1_netlist_a8e1798a2516c32fbab629ce8d60d4b1d}{addDevice}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}),
|
||
OpenChams::Name(\textcolor{stringliteral}{"Transistor"}), 2, OpenChams::Name(\textcolor{stringliteral}{"PMOS"}), \textcolor{keyword}{true});
|
||
inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
inst\_pmos1->addConnector(OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
\hyperlink{class_open_chams_1_1_transistor}{OpenChams::Transistor}* tr\_pmos1 = inst\_pmos1->
|
||
\hyperlink{class_open_chams_1_1_device_ad45d34f8765dd113a5b12289efe66c07}{addTransistor}(OpenChams::Name(\textcolor{stringliteral}{"m1"}));
|
||
tr\_pmos1->\hyperlink{class_open_chams_1_1_transistor_a705b53a51f0e265533b228f6e8beaf50}{setGate} (OpenChams::Name(\textcolor{stringliteral}{"G"})); \textcolor{comment}{// the name of the connector of inst\_pmos1}
|
||
tr\_pmos1->\hyperlink{class_open_chams_1_1_transistor_abc4a5d86e639ea13e27551722e2f9c17}{setSource}(OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
tr\_pmos1->\hyperlink{class_open_chams_1_1_transistor_a72ff8491040e3fdc1c8bd62b2392ab82}{setDrain} (OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
tr\_pmos1->\hyperlink{class_open_chams_1_1_transistor_a1484abe63e3f8ffbc2911c5230fa7091}{setBulk} (OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
\textcolor{comment}{// nets}
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* \_vdd = netlist->\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}(OpenChams::Name(\textcolor{stringliteral}{"vdd"}), OpenChams::Name(\textcolor{stringliteral}{"
|
||
power"}) , \textcolor{keyword}{true});
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* \_vss = netlist->\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}(OpenChams::Name(\textcolor{stringliteral}{"vss"}), OpenChams::Name(\textcolor{stringliteral}{"
|
||
ground"}) , \textcolor{keyword}{true});
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* \_in = netlist->\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}(OpenChams::Name(\textcolor{stringliteral}{"in"} ), OpenChams::Name(\textcolor{stringliteral}{"
|
||
logical"}), \textcolor{keyword}{true});
|
||
\hyperlink{class_open_chams_1_1_net}{OpenChams::Net}* \_out = netlist->\hyperlink{class_open_chams_1_1_netlist_a52be455a704925328843770552eca43d}{addNet}(OpenChams::Name(\textcolor{stringliteral}{"out"}), OpenChams::Name(\textcolor{stringliteral}{"
|
||
logical"}), \textcolor{keyword}{true});
|
||
\_vdd->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
\_vss->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
\_in->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo} (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
\_in->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo} (OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
\_out->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
\_out->\hyperlink{class_open_chams_1_1_net_a40c2c019175ba3bfa4b90f4ad5d06483}{connectTo}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
|
||
\textcolor{comment}{// schematic}
|
||
\hyperlink{class_open_chams_1_1_schematic}{OpenChams::Schematic}* schematic = circuit->
|
||
\hyperlink{class_open_chams_1_1_circuit_a57a79a9916df4512648bb195decb7250}{createSchematic}();
|
||
schematic->\hyperlink{class_open_chams_1_1_schematic_ac7fc9f5cdf1e22c53d42e6606e1af8ef}{addInstance}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), 2490, 2600, OpenChams::Name(\textcolor{stringliteral}{"ID"}));
|
||
schematic->\hyperlink{class_open_chams_1_1_schematic_ac7fc9f5cdf1e22c53d42e6606e1af8ef}{addInstance}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), 2490, 2300, OpenChams::Name(\textcolor{stringliteral}{"ID"}));
|
||
\_vdd->\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}(OpenChams::Name(\textcolor{stringliteral}{"inV"}), 0, 2490, 2100, OpenChams::Name(\textcolor{stringliteral}{"ID"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wVdd = \_vdd->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wVdd->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
wVdd->setEndPoint (0);
|
||
\_vss->\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}(OpenChams::Name(\textcolor{stringliteral}{"inV"}), 0, 2490, 2800, OpenChams::Name(\textcolor{stringliteral}{"MY"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wVss = \_vss->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wVss->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"S"}));
|
||
wVss->setEndPoint (0);
|
||
\_in->\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}(OpenChams::Name(\textcolor{stringliteral}{"inH"}), 0, 2190, 2500, OpenChams::Name(\textcolor{stringliteral}{"ID"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wIn = \_in->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wIn->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
wIn->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wIn1 = \_in->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wIn1->setStartPoint(0);
|
||
wIn1->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"G"}));
|
||
\_out->\hyperlink{class_open_chams_1_1_net_af395a7c9d6f3c2b24500b91260873664}{addPort}(OpenChams::Name(\textcolor{stringliteral}{"outH"}), 0, 2600, 2500, OpenChams::Name(\textcolor{stringliteral}{"ID"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wOut = \_out->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wOut->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
wOut->setEndPoint (OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
\hyperlink{class_open_chams_1_1_wire}{OpenChams::Wire}* wOut1 = \_out->\hyperlink{class_open_chams_1_1_net_a643a969f62770301b8b70ed63c36a55e}{addWire}();
|
||
wOut1->setStartPoint(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"D"}));
|
||
wOut1->setEndPoint (0);
|
||
|
||
\textcolor{comment}{// sizing}
|
||
\hyperlink{class_open_chams_1_1_sizing}{OpenChams::Sizing}* sizing = circuit->createSizing();
|
||
\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}* op\_pmos1 = sizing->\hyperlink{class_open_chams_1_1_sizing_a712e045c11e463cff8411b3d0fd7f732}{addOperator}(OpenChams::Name(\textcolor{stringliteral}{"
|
||
pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"OPVG(Veg)"}), OpenChams::Name(\textcolor{stringliteral}{"BSIM3V3"}));
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Temp"}), OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"temp"}));
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Ids"}) );
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"L"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"L"}) );
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Veg"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Veg"}) );
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vd"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) , 0.
|
||
5);
|
||
op\_pmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vs"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"}) );
|
||
\hyperlink{class_open_chams_1_1_operator}{OpenChams::Operator}* op\_nmos1 = sizing->\hyperlink{class_open_chams_1_1_sizing_a712e045c11e463cff8411b3d0fd7f732}{addOperator}(OpenChams::Name(\textcolor{stringliteral}{"
|
||
nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"OPW(Vg,Vs)"}), OpenChams::Name(\textcolor{stringliteral}{"BSIM3V3"}));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Temp"}), OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"temp"}));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Ids"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Ids"} ));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"L"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"L"} ));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vs"}) , OpenChams::Name(\textcolor{stringliteral}{"design"}), OpenChams::Name(\textcolor{stringliteral}{"Vdd"} ));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vg"}) , OpenChams::Name(\textcolor{stringliteral}{"pmos1"}) , OpenChams::Name(\textcolor{stringliteral}{"Vg"} ));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"Vd"}) , OpenChams::Name(\textcolor{stringliteral}{"pmos1"}) , OpenChams::Name(\textcolor{stringliteral}{"Vd"} ));
|
||
op\_nmos1->addConstraint(OpenChams::Name(\textcolor{stringliteral}{"another"}), OpenChams::Name(\textcolor{stringliteral}{"myEq"}), -2.5 );
|
||
\textcolor{comment}{// layout}
|
||
\hyperlink{class_open_chams_1_1_layout}{OpenChams::Layout}* layout = circuit->\hyperlink{class_open_chams_1_1_circuit_a725a691b0117c4b913b54e7bfd92832f}{createLayout}();
|
||
layout->\hyperlink{class_open_chams_1_1_layout_a4cc1899e9b782de44700fa0e4ac477ef}{addInstance}(OpenChams::Name(\textcolor{stringliteral}{"pmos1"}), OpenChams::Name(\textcolor{stringliteral}{"Common transistor"}));
|
||
layout->\hyperlink{class_open_chams_1_1_layout_a4cc1899e9b782de44700fa0e4ac477ef}{addInstance}(OpenChams::Name(\textcolor{stringliteral}{"nmos1"}), OpenChams::Name(\textcolor{stringliteral}{"Rotate transistor"}));
|
||
\textcolor{comment}{// create hbtree}
|
||
\hyperlink{class_open_chams_1_1_group}{OpenChams::Group}* g1 = \textcolor{keyword}{new} \hyperlink{class_open_chams_1_1_group}{OpenChams::Group}(\textcolor{stringliteral}{"g1"}); \textcolor{comment}{// default position
|
||
is NONE and default parent is NULL}
|
||
g1->\hyperlink{class_open_chams_1_1_group_a9fc27b2bc4da99c723102153c4fbf1c0}{setAlign}(OpenChams::Group::VERTICAL);
|
||
\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}* b1 = \textcolor{keyword}{new} \hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}(\textcolor{stringliteral}{"nmos1"}, OpenChams::Node::NONE,
|
||
g1);
|
||
g1->\hyperlink{class_open_chams_1_1_group_adc93b900e943312e905182fe44f21225}{setRootNode}(b1); \textcolor{comment}{// b1 is root node of group g1}
|
||
\hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}* b2 = \textcolor{keyword}{new} \hyperlink{class_open_chams_1_1_bloc}{OpenChams::Bloc}(\textcolor{stringliteral}{"pmos1"}, OpenChams::Node::TOP,
|
||
b1);
|
||
b1->\hyperlink{class_open_chams_1_1_node_a32e2fbbb73c6b7ee4a30189cc30106bf}{setTop}(b2); \textcolor{comment}{// b2 is on top of b1}
|
||
layout->\hyperlink{class_open_chams_1_1_layout_a6d828958e0faf1346b27276eab101858}{setHBTreeRoot}(g1); \textcolor{comment}{// g1 is the root of the tree}
|
||
|
||
circuit->\hyperlink{class_open_chams_1_1_circuit_a2eb07935ec946a07edcee2255b781193}{writeToFile}(\textcolor{stringliteral}{"./myInverter.xml"});
|
||
\textcolor{keywordflow}{return} 0;
|
||
\}
|
||
|
||
\end{DoxyCodeInclude}
|
||
|
||
|
||
\begin{DoxyNote}{Note}
|
||
In order to compile these codes, a C\-Make\-Lists.\-txt file is provided. User must set the \$\-V\-L\-S\-I\-S\-A\-P\-D\-\_\-\-T\-O\-P variable before running these commands in the directory containing the C\-Make\-Lists.\-txt file\-:
|
||
\begin{DoxyCode}
|
||
%> mkdir build; cd build
|
||
%> cmake ..
|
||
%> make
|
||
\end{DoxyCode}
|
||
|
||
\end{DoxyNote}
|
||
\hypertarget{openchams_openChamsPython}{}\subsection{Python}\label{openchams_openChamsPython}
|
||
\hypertarget{openchams_openChamsParsePython}{}\subsubsection{Parser}\label{openchams_openChamsParsePython}
|
||
The following python script ({\ttfamily parse\-Open\-Chams.\-py}) is an example of how to parse a O\-P\-E\-N\-C\-H\-A\-M\-S file using python module.
|
||
\begin{DoxyCodeInclude}
|
||
1 \textcolor{keyword}{import} sys
|
||
2
|
||
3 \textcolor{keyword}{from} OPENCHAMS \textcolor{keyword}{import} *
|
||
4
|
||
5 \textcolor{keyword}{def }printHBTree(node, indent):
|
||
6 \textcolor{keywordflow}{if} node == \textcolor{keywordtype}{None}:
|
||
7 \textcolor{keywordflow}{return}
|
||
8 \textcolor{keywordflow}{for} i \textcolor{keywordflow}{in} range(indent):
|
||
9 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" |"},
|
||
10 \textcolor{keywordflow}{if} isinstance(node, Bloc):
|
||
11 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" bloc:"}, node.getName(), \textcolor{stringliteral}{"-"}, node.getPosition()
|
||
12 printHBTree(node.top , indent+1)
|
||
13 printHBTree(node.right, indent+1)
|
||
14 \textcolor{keywordflow}{return}
|
||
15 \textcolor{keywordflow}{if} isinstance(node, Group):
|
||
16 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" group:"}, node.getName(), \textcolor{stringliteral}{"-"}, node.getPosition(), \textcolor{stringliteral}{"-"}, node.align, \textcolor{stringliteral}{"-"}, node.isolated, \textcolor{stringliteral}{"-"},
|
||
node.paired
|
||
17 printHBTree(node.rootNode, indent+1)
|
||
18 printHBTree(node.top , indent+1)
|
||
19 printHBTree(node.right , indent+1)
|
||
20 \textcolor{keywordflow}{return}
|
||
21
|
||
22 \textcolor{keyword}{def }printContents(circuit):
|
||
23 \textcolor{keywordflow}{print} circuit.name
|
||
24 \textcolor{comment}{# circuit parameters}
|
||
25 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + parameters"}
|
||
26 \textcolor{keywordflow}{for} param \textcolor{keywordflow}{in} circuit.parameters.getValues():
|
||
27 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, param.key, \textcolor{stringliteral}{":"}, param.value
|
||
28 \textcolor{keywordflow}{for} param \textcolor{keywordflow}{in} circuit.parameters.getEqValues():
|
||
29 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, param.key, \textcolor{stringliteral}{":"}, param.value
|
||
30 \textcolor{comment}{# netlist}
|
||
31 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + netlist"}
|
||
32 \textcolor{comment}{# instances}
|
||
33 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instances"}
|
||
34 \textcolor{keywordflow}{for} instance \textcolor{keywordflow}{in} circuit.netlist.getInstances():
|
||
35 \textcolor{keywordflow}{if} isinstance(instance, Device):
|
||
36 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, instance.name, \textcolor{stringliteral}{":"}, instance.model, instance.order, instance.mosType,
|
||
instance.sourceBulkConnected
|
||
37 \textcolor{keywordflow}{else}:
|
||
38 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, instance.name, \textcolor{stringliteral}{":"}, instance.model, instance.order
|
||
39 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + connectors"}
|
||
40 \textcolor{keywordflow}{for} conn \textcolor{keywordflow}{in} instance.getConnectors():
|
||
41 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | |"}, conn.key, \textcolor{stringliteral}{":"}, conn.value.name
|
||
42 \textcolor{keywordflow}{if} isinstance(instance, Device):
|
||
43 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + transistors"}
|
||
44 \textcolor{keywordflow}{for} tr \textcolor{keywordflow}{in} instance.getTransistors():
|
||
45 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | | name:"}, tr.name, \textcolor{stringliteral}{"- gate:"}, tr.gate, \textcolor{stringliteral}{"- source:"}, tr.source, \textcolor{stringliteral}{"- drain:"}, tr.drain, \textcolor{stringliteral}{
|
||
"- bulk:"}, tr.bulk
|
||
46 \textcolor{comment}{# nets}
|
||
47 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + nets"}
|
||
48 schematicNet = \textcolor{keyword}{False}
|
||
49 \textcolor{keywordflow}{for} net \textcolor{keywordflow}{in} circuit.netlist.getNets():
|
||
50 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | +"}, net.name, \textcolor{stringliteral}{":"}, net.type, net.external
|
||
51 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | + connections"}
|
||
52 \textcolor{keywordflow}{for} conn \textcolor{keywordflow}{in} net.getConnections():
|
||
53 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | | | %s.%s"}%(conn.instanceName, conn.connectorName)
|
||
54 \textcolor{keywordflow}{if} \textcolor{keywordflow}{not} net.hasNoPorts() \textcolor{keywordflow}{or} \textcolor{keywordflow}{not} net.hasNoWires():
|
||
55 schematicNet = \textcolor{keyword}{True}
|
||
56 \textcolor{comment}{# schematic}
|
||
57 \textcolor{keywordflow}{if} (circuit.schematic):
|
||
58 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + schematic"}
|
||
59 \textcolor{keywordflow}{for} instance \textcolor{keywordflow}{in} circuit.schematic.getInstances():
|
||
60 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instance name:"}, instance.key, \textcolor{stringliteral}{"- x:"}, instance.value.x, \textcolor{stringliteral}{"- y:"}, instance.value.y, \textcolor{stringliteral}{"-
|
||
orientation:"}, instance.value.orientation
|
||
61 \textcolor{keywordflow}{if} schematicNet:
|
||
62 \textcolor{keywordflow}{for} net \textcolor{keywordflow}{in} circuit.netlist.getNets():
|
||
63 \textcolor{keywordflow}{if} net.hasNoPorts() \textcolor{keywordflow}{and} net.hasNoWires():
|
||
64 \textcolor{keywordflow}{continue}
|
||
65 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + net name:"}, net.name
|
||
66 \textcolor{keywordflow}{for} port \textcolor{keywordflow}{in} net.getPorts():
|
||
67 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + port type:"}, port.type, \textcolor{stringliteral}{"- idx:"}, port.index, \textcolor{stringliteral}{"- x:"}, port.x, \textcolor{stringliteral}{"- y:"}, port.y, \textcolor{stringliteral}{"
|
||
- orientation:"}, port.orientation
|
||
68 \textcolor{keywordflow}{for} wire \textcolor{keywordflow}{in} net.getWires():
|
||
69 \textcolor{keywordflow}{if} isinstance(wire.startPoint, InstancePoint):
|
||
70 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + wire <"} + wire.startPoint.name.getString() + \textcolor{stringliteral}{","} +
|
||
wire.startPoint.plug.getString() +\textcolor{stringliteral}{">"}
|
||
71 \textcolor{keywordflow}{elif} isinstance(wire.startPoint, PortPoint):
|
||
72 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + wire <"} + str(wire.startPoint.index) + \textcolor{stringliteral}{">"}
|
||
73 \textcolor{keywordflow}{else}:
|
||
74 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" - - UNKNOWN START POINT"}
|
||
75 \textcolor{keywordflow}{for} point \textcolor{keywordflow}{in} wire.getIntermediatePoints():
|
||
76 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + str(point.x) + \textcolor{stringliteral}{","} + str(point.y) + \textcolor{stringliteral}{">"}
|
||
77 \textcolor{keywordflow}{if} isinstance(wire.endPoint, InstancePoint):
|
||
78 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + wire.endPoint.name.getString() + \textcolor{stringliteral}{","} +
|
||
wire.endPoint.plug.getString() +\textcolor{stringliteral}{">"}
|
||
79 \textcolor{keywordflow}{elif} isinstance(wire.endPoint, PortPoint):
|
||
80 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | <"} + str(wire.endPoint.index) + \textcolor{stringliteral}{">"}
|
||
81 \textcolor{keywordflow}{else}:
|
||
82 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" - - UNKNOWN END POINT"}
|
||
83 \textcolor{comment}{# sizing}
|
||
84 \textcolor{keywordflow}{if} (circuit.sizing):
|
||
85 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + sizing"}
|
||
86 \textcolor{keywordflow}{for} op \textcolor{keywordflow}{in} circuit.sizing.getOperators():
|
||
87 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + instance name:"}, op.key, \textcolor{stringliteral}{"- operator:"}, op.value.name, \textcolor{stringliteral}{"- simulModel:"},
|
||
op.value.simulModel
|
||
88 \textcolor{keywordflow}{for} constraint \textcolor{keywordflow}{in} op.value.getConstraints():
|
||
89 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | + param:"}, constraint.key, \textcolor{stringliteral}{"- ref:"}, constraint.value.ref, \textcolor{stringliteral}{"- refParam:"},
|
||
constraint.value.refParam, \textcolor{stringliteral}{"- factor:"}, constraint.value.factor
|
||
90 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + equations"}
|
||
91 \textcolor{keywordflow}{for} eq \textcolor{keywordflow}{in} circuit.sizing.getEquations():
|
||
92 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | |"}, eq.key, \textcolor{stringliteral}{":"}, eq.value
|
||
93 \textcolor{comment}{# layout}
|
||
94 \textcolor{keywordflow}{if} (circuit.layout):
|
||
95 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" + layout"}
|
||
96 \textcolor{keywordflow}{for} inst \textcolor{keywordflow}{in} circuit.layout.getInstances():
|
||
97 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | | instance name:"}, inst.key, \textcolor{stringliteral}{"- style:"}, inst.value
|
||
98 \textcolor{keywordflow}{if} circuit.layout.hbTreeRoot != \textcolor{keywordtype}{None}:
|
||
99 \textcolor{keywordflow}{print} \textcolor{stringliteral}{" | + hbtree"}
|
||
100 printHBTree(circuit.layout.hbTreeRoot, 2)
|
||
101
|
||
102 \textcolor{keyword}{def }usage():
|
||
103 \textcolor{keywordflow}{print} \textcolor{stringliteral}{"usage:"}, sys.argv[0], \textcolor{stringliteral}{"[filename]"}
|
||
104 sys.exit(48)
|
||
105
|
||
106 \textcolor{keyword}{def }main():
|
||
107 \textcolor{keywordflow}{if} len(sys.argv) == 1:
|
||
108 filename = \textcolor{stringliteral}{"./inverter.xml"}
|
||
109 \textcolor{keywordflow}{elif} len(sys.argv) == 2:
|
||
110 filename = sys.argv[1]
|
||
111 \textcolor{keywordflow}{else}:
|
||
112 usage()
|
||
113
|
||
114 circuit = Circuit.readFromFile(filename)
|
||
115 printContents(circuit)
|
||
116
|
||
117
|
||
118 \textcolor{keywordflow}{if} \_\_name\_\_ == \textcolor{stringliteral}{"\_\_main\_\_"}:
|
||
119 main()
|
||
120
|
||
\end{DoxyCodeInclude}
|
||
\hypertarget{openchams_openChamsDrivePython}{}\subsubsection{Driver}\label{openchams_openChamsDrivePython}
|
||
This python script ({\ttfamily drive\-Open\-Chams.\-py}) generates an inverter.\-xml file equivalent to the included one.
|
||
\begin{DoxyCodeInclude}
|
||
1 \textcolor{keyword}{from} OPENCHAMS \textcolor{keyword}{import} *
|
||
2
|
||
3 circuit = Circuit(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"design"}), \hyperlink{class_name}{Name}(\textcolor{stringliteral}{"myTech"}))
|
||
4 \textcolor{comment}{# value parameters}
|
||
5 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"temp"}), 27.0 )
|
||
6 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"Vdd"}) , 1.2 )
|
||
7 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"Vss"}) , 0.0 )
|
||
8 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"L"}) , 0.1e-6)
|
||
9 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"Ids"}) , 30e-6 )
|
||
10 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"Veg"}) , 0.12 )
|
||
11 \textcolor{comment}{# equation parameters}
|
||
12 circuit.addParameter(\hyperlink{class_name}{Name}(\textcolor{stringliteral}{"complex"}), \textcolor{stringliteral}{"myEq"})
|
||
13
|
||
14 \textcolor{comment}{# netlist :}
|
||
15 netlist = circuit.createNetlist()
|
||
16 \textcolor{comment}{# instances}
|
||
17 \textcolor{comment}{# nmos1}
|
||
18 inst\_nmos1 = netlist.addDevice(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"Transistor"}, 1, \textcolor{stringliteral}{"NMOS"}, \textcolor{keyword}{True})
|
||
19 inst\_nmos1.addConnector(\textcolor{stringliteral}{"G"})
|
||
20 inst\_nmos1.addConnector(\textcolor{stringliteral}{"S"})
|
||
21 inst\_nmos1.addConnector(\textcolor{stringliteral}{"D"})
|
||
22 tr\_nmos1 = inst\_nmos1.addTransistor(\textcolor{stringliteral}{"m1"})
|
||
23 tr\_nmos1.gate = \textcolor{stringliteral}{"G"} \textcolor{comment}{# the name of the connector of inst\_nmos1}
|
||
24 tr\_nmos1.source = \textcolor{stringliteral}{"S"}
|
||
25 tr\_nmos1.drain = \textcolor{stringliteral}{"D"}
|
||
26 tr\_nmos1.bulk = \textcolor{stringliteral}{"S"}
|
||
27 \textcolor{comment}{# pmos1}
|
||
28 inst\_pmos1 = netlist.addDevice(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"Transistor"}, 2, \textcolor{stringliteral}{"PMOS"}, \textcolor{keyword}{True})
|
||
29 inst\_pmos1.addConnector(\textcolor{stringliteral}{"G"})
|
||
30 inst\_pmos1.addConnector(\textcolor{stringliteral}{"S"})
|
||
31 inst\_pmos1.addConnector(\textcolor{stringliteral}{"D"})
|
||
32 tr\_pmos1 = inst\_pmos1.addTransistor(\textcolor{stringliteral}{"m1"})
|
||
33 tr\_pmos1.gate = \textcolor{stringliteral}{"G"} \textcolor{comment}{# the name of the connector of inst\_pmos1}
|
||
34 tr\_pmos1.source = \textcolor{stringliteral}{"S"}
|
||
35 tr\_pmos1.drain = \textcolor{stringliteral}{"D"}
|
||
36 tr\_pmos1.bulk = \textcolor{stringliteral}{"S"}
|
||
37 \textcolor{comment}{# nets}
|
||
38 \_vdd = netlist.addNet(\textcolor{stringliteral}{"vdd"}, \textcolor{stringliteral}{"power"} , \textcolor{keyword}{True})
|
||
39 \_vss = netlist.addNet(\textcolor{stringliteral}{"vss"}, \textcolor{stringliteral}{"ground"} , \textcolor{keyword}{True})
|
||
40 \_in = netlist.addNet(\textcolor{stringliteral}{"in"} , \textcolor{stringliteral}{"logical"}, \textcolor{keyword}{True})
|
||
41 \_out = netlist.addNet(\textcolor{stringliteral}{"out"}, \textcolor{stringliteral}{"logical"}, \textcolor{keyword}{True})
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42 \_vdd.connectTo(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"S"})
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43 \_vss.connectTo(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"S"})
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44 \_in.connectTo (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"G"})
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45 \_in.connectTo (\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"})
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46 \_out.connectTo(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"})
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||
47 \_out.connectTo(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"D"})
|
||
48 \textcolor{comment}{# schematic}
|
||
49 schematic = circuit.createSchematic()
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||
50 schematic.addInstance(\textcolor{stringliteral}{"nmos1"}, 2490, 2600, \textcolor{stringliteral}{"ID"})
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||
51 schematic.addInstance(\textcolor{stringliteral}{"pmos1"}, 2490, 2300, \textcolor{stringliteral}{"ID"})
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52 \_vdd.addPort(\textcolor{stringliteral}{"inV"} , 0, 2490, 2100, \textcolor{stringliteral}{"ID"})
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53 \_vss.addPort(\textcolor{stringliteral}{"inV"} , 0, 2490, 2800, \textcolor{stringliteral}{"MY"})
|
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54 \_in.addPort (\textcolor{stringliteral}{"inH"} , 0, 2190, 2500, \textcolor{stringliteral}{"ID"})
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||
55 \_out.addPort(\textcolor{stringliteral}{"outH"}, 0, 2600, 2500, \textcolor{stringliteral}{"ID"})
|
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56 wireVdd = \_vdd.addWire()
|
||
57 wireVdd.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"S"})
|
||
58 wireVdd.setEndPoint(0)
|
||
59 wireVss = \_vss.addWire()
|
||
60 wireVss.setStartPoint(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"S"})
|
||
61 wireVss.setEndPoint(0)
|
||
62 wireIn0 = \_in.addWire()
|
||
63 wireIn1 = \_in.addWire()
|
||
64 wireIn0.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"})
|
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65 wireIn0.setEndPoint (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"G"})
|
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66 wireIn1.setStartPoint(0)
|
||
67 wireIn1.setEndPoint (\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"G"})
|
||
68 wireOut0 = \_out.addWire()
|
||
69 wireOut1 = \_out.addWire()
|
||
70 wireOut0.setStartPoint(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"D"})
|
||
71 wireOut0.setEndPoint (\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"})
|
||
72 wireOut1.setStartPoint(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"D"})
|
||
73 wireOut1.setEndPoint (0)
|
||
74 \textcolor{comment}{# sizing}
|
||
75 sizing = circuit.createSizing()
|
||
76 op\_pmos1 = sizing.addOperator(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"OPVG(Veg)"} , \textcolor{stringliteral}{"BSIM3V3"})
|
||
77 op\_pmos1.addConstraint(\textcolor{stringliteral}{"Temp"}, \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"temp"})
|
||
78 op\_pmos1.addConstraint(\textcolor{stringliteral}{"Ids"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Ids"} )
|
||
79 op\_pmos1.addConstraint(\textcolor{stringliteral}{"L"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"L"} )
|
||
80 op\_pmos1.addConstraint(\textcolor{stringliteral}{"Veg"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Veg"} )
|
||
81 op\_pmos1.addConstraint(\textcolor{stringliteral}{"Vd"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"}, 0.5)
|
||
82 op\_pmos1.addConstraint(\textcolor{stringliteral}{"Vs"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"} )
|
||
83 op\_nmos1 = sizing.addOperator(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"OPW(Vg,Vs)"}, \textcolor{stringliteral}{"BSIM3V3"})
|
||
84 op\_nmos1.addConstraint(\textcolor{stringliteral}{"Temp"}, \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"temp"})
|
||
85 op\_nmos1.addConstraint(\textcolor{stringliteral}{"Ids"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Ids"} )
|
||
86 op\_nmos1.addConstraint(\textcolor{stringliteral}{"L"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"L"} )
|
||
87 op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vs"} , \textcolor{stringliteral}{"design"}, \textcolor{stringliteral}{"Vdd"} )
|
||
88 op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vg"} , \textcolor{stringliteral}{"pmos1"} , \textcolor{stringliteral}{"Vg"} )
|
||
89 op\_nmos1.addConstraint(\textcolor{stringliteral}{"Vd"} , \textcolor{stringliteral}{"pmos1"} , \textcolor{stringliteral}{"Vd"} )
|
||
90 op\_nmos1.addConstraint(\textcolor{stringliteral}{"another"}, \textcolor{stringliteral}{"myEq"}, -2.5 )
|
||
91 \textcolor{comment}{# layout}
|
||
92 layout = circuit.createLayout()
|
||
93 layout.addInstance(\textcolor{stringliteral}{"pmos1"}, \textcolor{stringliteral}{"Common transistor"})
|
||
94 layout.addInstance(\textcolor{stringliteral}{"nmos1"}, \textcolor{stringliteral}{"Rotate transistor"})
|
||
95 \textcolor{comment}{# create hbtree}
|
||
96 g1 = Group(\textcolor{stringliteral}{"g1"})
|
||
97 g1.align = Group.Align.VERTICAL
|
||
98 b1 = Bloc(\textcolor{stringliteral}{"nmos1"}, Node.Position.NONE, g1)
|
||
99 g1.rootNode = b1
|
||
100 b2 = Bloc(\textcolor{stringliteral}{"pmos1"}, Node.Position.TOP, b1)
|
||
101 b1.top = b2
|
||
102 layout.hbTreeRoot = g1
|
||
103
|
||
104 circuit.writeToFile(\textcolor{stringliteral}{"./myInverter.xml"})
|
||
\end{DoxyCodeInclude}
|
||
|
||
|
||
\begin{DoxyNote}{Note}
|
||
In order to run these two scripts ({\ttfamily parse\-Open\-Chams.\-py} \& drive\-Open\-Chams.\-py), user must ensure that \$\-P\-Y\-T\-H\-O\-N\-P\-A\-T\-H variable points to the directory containing O\-P\-E\-N\-C\-H\-A\-M\-S.\-so module.
|
||
\end{DoxyNote}
|