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<A NAME="CHILD_LINKS"><STRONG>Sous-sections</STRONG></A>
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<LI><A NAME="tex2html46"
HREF="node2.html#SECTION00021000000000000000">Synopsys</A>
<LI><A NAME="tex2html47"
HREF="node2.html#SECTION00022000000000000000">Description</A>
<LI><A NAME="tex2html48"
HREF="node2.html#SECTION00023000000000000000">Parameters</A>
<LI><A NAME="tex2html49"
HREF="node2.html#SECTION00024000000000000000">Attributes</A>
<LI><A NAME="tex2html50"
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<H1><A NAME="SECTION00020000000000000000"></A>
<A NAME="secnet"></A>
<BR>
Nets
</H1>
<H2><A NAME="SECTION00021000000000000000">
Synopsys</A>
</H2>
<P>
<PRE>
netInput = LogicIn ( name, arity )
</PRE>
<P>
<H2><A NAME="SECTION00022000000000000000">
Description</A>
</H2>
<P>
Instanciation of net. Differents kind of nets are listed below :
<UL>
<LI><code>LogicIn</code> : Creation of an input port
</LI>
<LI><code>LogicOut</code> : Creation of an output port
</LI>
<LI><code>LogicInOut</code> : Creation of an inout port
</LI>
<LI><code>LogicUnknown</code> : Creation of an input/output port which direction is not defined
</LI>
<LI><code>TriState</code> : Creation of a tristate port
</LI>
<LI><code>CkIn</code> : Creation of a clock port
</LI>
<LI><code>VddIn</code> : Creation of the vdd alimentation
</LI>
<LI><code>VssIn</code> : Creation of the vss alimentation
</LI>
<LI><code>Signal</code> : Creation of an internal net
</LI>
</UL>
<P>
<H2><A NAME="SECTION00023000000000000000">
Parameters</A>
</H2>
<P>
<UL>
<LI><code>name</code> : Name of the net (mandatory argument)
</LI>
<LI><code>arity</code> : Arity of the net (mandatory argument)
</LI>
<LI><code>indice</code> : For buses only : the LSB bit (optional argument : set to 0 by default)
<BR></LI>
</UL>
<P>
Only <code>CkIn, </code><code>VddIn</code> and <code>VssIn</code> do not have the same parameters : there is only the <code>name</code> parameter (they are 1 bit nets).
<P>
<H2><A NAME="SECTION00024000000000000000">
Attributes</A>
</H2>
<P>
<UL>
<LI><code>_name</code> : Name of the net
</LI>
<LI><code>_arity</code> : Arity of the net (by default set to 0)
</LI>
<LI><code>_ind</code> : LSB of the net
</LI>
<LI><code>_ext</code> : Tells if the net is external or not (True/False)
</LI>
<LI><code>_direct</code> : If the net is external, tells the direction ("IN", "OUT", "INOUT", "TRISTATE", "UNKNOWN")
</LI>
<LI><code>_h_type</code> : If the net is an alimentation or a clock, tells the type ("POWER", "GROUND", "CLOCK")
</LI>
<LI><code>_type</code> : The arithmetic type of the net ( "nr" )
</LI>
<LI><code>_st_cell</code> : The stratus cell which the net is instanciated in
</LI>
<LI><code>_real_net</code> : If the net is a part of a net (Sig) it is the real net corresponding
</LI>
<LI><code>_alias</code> : [] by default. When the net has an alias, it's a tab. Each element of the tab correspond to a bit of the net (from the LSB to the MSB), it'a a dictionnary : the only key is the net which this net is an alias from, the value is the bit of the net
</LI>
<LI><code>_to_merge</code> : [] by default. The same as _alias
</LI>
<LI><code>_to_cat</code> : [] by default. The same as _alias
<BR></LI>
</UL>
<P>
And, in connection with Hurricane :
<UL>
<LI><code>_hur_net</code> : A tab with all the hurricane nets corresponding to the stratus net ; From the LSB to the MSB (for example, with a 1 bit net, one gets the hurricane net by doing : <code>net._hur_net[0]</code> ).
</LI>
</UL>
<P>
<H2><A NAME="SECTION00025000000000000000">
Methods</A>
</H2>
<P>
<UL>
<LI><code>Buffer</code> : Instanciation of a Buffer
</LI>
<LI><code>Shift</code> : Instanciation of a shifter
</LI>
<LI><code>Mux</code> : Instanciation of a multiplexor
</LI>
<LI><code>Reg</code> : Instanciation of a register
</LI>
<LI><code>Eq/Ne</code> : Instanciation of comparison generator
</LI>
<LI><code>Extend</code> : A net is extended
</LI>
<LI><code>Alias</code> : A net is an alias of another net
</LI>
<LI><code>Delete</code> : Deletion of the Hurricane nets
<BR></LI>
</UL>
And the overloards :
<UL>
<LI>__init__ : Initialisation of nets
</LI>
<LI>__le__ : initialisation of a net thanks to &lt;= notation
</LI>
<LI>__getitem__, __geslice__ : Creation of "Sig" nets : which are part of nets (use of <code>[]</code> and <code>[:]</code>)
</LI>
<LI>__and__, __or__, __xor__, __invert__ : boolean operation with &amp;, |, ,&nbsp;
</LI>
<LI>__add__, __mul__, __div__ : arithmetic operators with +, * and /
</LI>
</UL>
<P>
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<ADDRESS>
Sophie <small>BELLOEIL</small><br>20051116.1
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