110 lines
4.2 KiB
ReStructuredText
110 lines
4.2 KiB
ReStructuredText
.. -*- Mode: rst -*-
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=============================
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Coriolis |VLSI| Backend Tools
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=============================
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:slug: homepage
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:date: 2019-12-20 16:00
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:author: Jean-Paul Chaput
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:Contact: <Jean-Paul.Chaput@lip6.fr>
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:Version: June 4, 2019 (jpc)
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.. include:: ../../etc/definitions.rst
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.. contents::
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Abstract
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========
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.. image:: {attach}/images/common/amd2901_chip_routed.png
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:width: 50%
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:align: center
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:alt: Routed AM2901 layout picture.
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|Alliance| is a complete toolchain for |VLSI| design. It provides a |VHDL| compiler
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and simulator, logic synthetiser, automatic place & route and portable |CMOS|
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library. It has been in used in research projects such as the 875K transistors
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|StaCS| superscalar microprocessor or the 400K transistors |IEEE| gigabit |HSL|
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router. It has been actively developped during the 1990-2000 years and is maintained
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since. Its practical limit for one standard cell block (flat) is about 10K gates,
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above that limit you would need to use hierarchy and manually build a floorplan.
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|Alliance| is entirely written in C.
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|Coriolis| was started in the year 2000 as a replacement for the place & route stage
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of |Alliance|. As such it is able to handle standard cells block (flat) of at least 150K
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gates. It was later extended to support analog design re-implementing the methodology
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introduced by the |CIAN| team of |LIP6| / |SU| in |CAIRO| / |CAIRO+|. The tools have
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been designed from the ground up to support digital only, analog only or mixed circuits.
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|Coriolis| is written in a mix of C++ and |Python|.
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|Alliance| / |Coriolis| is free software. All source code is realeased under the GPL_
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license, except for |Hurricane| which is under LGPL_ and the Si2_ |LEF| / |DEF|
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parser drivers that are under `Apache License, Version 2.0`_.
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`Short introduction to Symbolic Layout. <{filename}/pages/symbolic-layout.rst>`_
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Design Flow
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~~~~~~~~~~~
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We are also upgrading the complete design flow by replacing |Alliance| obsoleting
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tools by more advanced |FOSS| alternatives:
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* Yosys_ for logical synthesis.
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* GHDL_ for |VHDL| simulation.
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Design & Features of |Coriolis|
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===============================
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The |Coriolis| toolchain is build upon the |Hurricane| database.
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* **Tool Integration.** To better manages the challenges arising in the
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increasingly bigger designs, the various tools have to work together
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as a whole, in a tight integration at runtime. The |Hurricane| database
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has been develop to address this problem and as a results, all |Coriolis|
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tools are built upon it and can communicate through that core database.
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* **Deterministic.** The database and the tools are completely deterministics.
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Two runs in *exactly* the same context gives the same result.
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* **C++ & Python.** The |Hurricane| database and all tools are fully exported
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in |Python| providing a seamless integration. The whole toolchain is build
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as a mix of C++ for computational intensive part and |Python| scripts for
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everything else. There is not even a binary, the main program *is* a
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|Python| script and can be rewritten in any way you like.
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* **Graphic Interface.** |Hurricane| also come with a graphical interface
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allowing to display, explore or check your design. The graphic interface
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can be extended (in C++) do display any custom overlay.
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* **Symbolic Layout.** For digital part of the designs, we use a symbolic
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layer approach. Note that |Coriolis| can make digital designs using real
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technology, but it's a largely untested feature yet.
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* **Analog Design.** A complete user-guided methodology for designing analog
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circuits is available. It is fully integrated in all the tools and will
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allow mixed design in the near future.
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Disclaimer
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==========
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|Alliance| / |Coriolis| tools, at the time being, are not suitable for deep submicron
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technological nodes (below 130nm / 180nm).
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For portability across foundries, technological nodes and freedom from fondries |NDA|,
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|Alliance| / |Coriolis| rely on *portable* layout (or *scalable* layout, or *symbolic* layout).
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To produce a valid |GDS| file, you would need to use the |s2r| translation tool which
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needs a configuration file suited for the target technology, and *that* file is under
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|NDA|. So, either should be written by you, or given to you through services like
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MyCMP_.
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