Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
.. -*- Mode: rst -*-
===============
Coriolis README
===============
Coriolis is a free database, placement tool and routing tool for VLSI design.
Purpose
=======
Coriolis provides several tools to perform the layout of VLSI circuits. Its
main components are the Hurricane database, the Etesian placer and the Katana
router, but other tools can use the Hurricane database and the parsers
provided.
The user interface <cgt> is the prefered way to use Coriolis, but all
Coriolis tools are Python modules and thus scriptable.
Documentation
=============
The complete documentation is available here, both in pdf & html:
./documentation/output/html
./documentation/UsersGuide/UsersGuide.pdf
The documentation of the latest *stable* version is also
available online. It may be quite outdated from the *devel*
version.
https://www-soc.lip6.fr/sesi-docs/coriolis2-docs/coriolis2/en/latex/users-guide/UsersGuide.pdf
Building Coriolis
=================
To build Coriolis, ensure the following prerequisites are met:
* Python 2.7.
* cmake.
* boost.
* bison & flex.
* Qt 4 or 5.
* libxml2.
* RapidJSON
* A C++11 compliant compiler.
The build system relies on a fixed directory tree from the root
of the user currently building it. Thus first step is to get a clone of
the repository in the right place. Proceed as follow: ::
ego@home:~$ mkdir -p ~/coriolis-2.x/src/support
ego@home:~$ cd ~/coriolis-2.x/src/support
ego@home:~$ git clone http://github.com/miloyip/rapidjson
ego@home:~$ git checkout ec322005072076ef53984462fb4a1075c27c7dfd
ego@home:~$ cd ~/coriolis-2.x/src
ego@home:src$ git clone https://www-soc.lip6.fr/git/coriolis.git
ego@home:src$ cd coriolis
If you want to use the *devel* branch: ::
ego@home:coriolis$ git checkout devel
Then, build the tool: ::
ego@home:coriolis$ make install
Coriolis gets installed at the root of the following tree: ::
~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/
Where ``<OS>`` is the name of your operating system and ``<DISTRIB>`` your
distribution.
Using Coriolis
==============
The Coriolis main interface can be launched with the command: ::
ego@home:~: ~/coriolis-2.x/<OS>.<DISTRIB>/Release.Shared/install/bin/coriolis
The ``coriolis`` script detects its location and setups the UNIX
environment appropriately, then lauches ``cgt`` (or *any* command, with the
``--run=<COMMAND>`` option).
Conversely, you can setup the current shell environement for Coriolis by
using the helper ``coriolisEnv.py``, then run any Coriolis tool: ::
ego@home:~$ eval `~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py`
ego@home:~$ cgt -V
29b57e86e5