192 lines
6.6 KiB
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192 lines
6.6 KiB
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original version by: Nikos Drakos, CBLU, University of Leeds
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* revised and updated by: Marcus Hennecke, Ross Moore, Herb Swan
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* with significant contributions from:
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Jens Lippmann, Marek Rouchal, Martin Wilck and others -->
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<TITLE>DpgenRf1d</TITLE>
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<H1><A NAME="SECTION000330000000000000000">
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DpgenRf1d</A>
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</H1>
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<UL>
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<LI><SPAN CLASS="textbf">Name</SPAN> : DpgenRf1d, DpgenRf1dr0 - Register File with Decoder Macro-Generator
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</LI>
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<LI><SPAN CLASS="textbf">Synopsys</SPAN> :
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<PRE>
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Generate ( 'DpgenRf1d', modelname
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, param = { 'nbit' : n
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, 'nword' : regNumber
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, 'physical' : True
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}
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)
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</PRE>
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</LI>
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<LI><SPAN CLASS="textbf">Description</SPAN> : Generates a register file of <code>regNumber</code> words of <code>n</code> bits with decoder named <code>modelname</code>.
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</LI>
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<LI><SPAN CLASS="textbf">Terminal Names</SPAN> :
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<UL>
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<LI><SPAN CLASS="textbf">ck</SPAN> : clock signal (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">sel</SPAN> : select the write bus (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">wen</SPAN> : write enable (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">ren</SPAN> : read enable (input, 1 bit)
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</LI>
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<LI><SPAN CLASS="textbf">adr</SPAN> : the read address (input, <code>Y</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">adw</SPAN> : the write address (input, <code>Y</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">datain0</SPAN> : first write bus (input, <code>n</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">datain1</SPAN> : second write bus (input, <code>n</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">dataout</SPAN> : read bus (output, <code>n</code> bits)
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</LI>
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<LI><SPAN CLASS="textbf">vdd</SPAN> : power
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</LI>
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<LI><SPAN CLASS="textbf">vss</SPAN> : ground
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</LI>
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</UL>
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</LI>
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<LI><SPAN CLASS="textbf">Parameters</SPAN> : Parameters are given in the map <code>param</code>.
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<UL>
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<LI><SPAN CLASS="textbf">nbit</SPAN> (mandatory) : Defines the size of the words (even, between 2 and 64)
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</LI>
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<LI><SPAN CLASS="textbf">nword</SPAN> (mandatory) : Defines the number of the words (even, between 6 and 32)
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</LI>
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<LI><SPAN CLASS="textbf">physical</SPAN> (optional, default value : False) : In order to generate a layout
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</LI>
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</UL>
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</LI>
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<LI><SPAN CLASS="textbf">How it works</SPAN> :
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<UL>
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<LI>datain0 and datain1 are the two write busses. Only one is used to actually write the register word, it is selected by the sel signal.
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</LI>
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<LI>When sel is set to zero datain0 is used to write the register word, otherwise it will be datain1
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</LI>
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<LI>adr, adw : the width (Y) of those signals is computed from regNumber : <code>Y = log2(regNumber)</code>
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</LI>
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<LI>wen and ren : write enable and read enable, allows reading and writing when sets to <code>one</code>
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</LI>
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<LI>The DpgenRf1dr0 variant differs from the DpgenRf1d in that the register of address zero is stuck to zero. You can write into it, it will not change the value. When read, it will always return zero
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</LI>
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</UL>
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</LI>
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<LI><SPAN CLASS="textbf">Example</SPAN> :
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<PRE>
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from stratus import *
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class inst_rf1d ( Model ) :
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def Interface ( self ) :
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self.ck = SignalIn ( "ck", 1 )
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self.sel = SignalIn ( "sel", 1 )
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self.wen = SignalIn ( "wen", 1 )
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self.ren = SignalIn ( "ren", 1 )
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self.adr = SignalIn ( "adr", 4 )
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self.adw = SignalIn ( "adw", 4 )
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self.datain0 = SignalIn ( "datain0", 4 )
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self.datain1 = SignalIn ( "datain1", 4 )
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self.dataout = SignalOut ( "dataout", 4 )
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self.vdd = VddIn ( "vdd" )
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self.vss = VssIn ( "vss" )
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def Netlist ( self ) :
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Generate ( 'DpgenRf1d', 'rf1d_4_16'
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, param = { 'nbit' : 4
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, 'nword' : 16
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, 'physical' : True
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}
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)
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self.I = Inst ( 'rf1d_4_16', 'inst'
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, map = { 'ck' : self.ck
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, 'sel' : self.sel
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, 'wen' : self.wen
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, 'ren' : self.ren
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, 'adr' : self.adr
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, 'adw' : self.adw
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, 'datain0' : self.datain0
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, 'datain1' : self.datain1
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, 'dataout' : self.dataout
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, 'vdd' : self.vdd
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, 'vss' : self.vss
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}
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)
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def Layout ( self ) :
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Place ( self.I, NOSYM, Ref(0, 0) )
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</PRE>
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</LI>
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</UL>
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<DIV CLASS="navigation">
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<p>
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<hr><table align="center" width="100%" cellpadding="0" cellspacing="2">
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<tr><td class="navigation" align="left" width="33%"><B>Previous</B></td>
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<td class="navigation" align="center" width="34%"><B>Up</B></td>
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<td class="navigation" align="right" width="33%"><B>Next</B></td>
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</tr><tr>
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<td class="navigation" align="left" width="33%"><A HREF="node32.html">DpgenRf1</A></td>
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<td class="navigation" align="center" width="34%"><A HREF="dpgen.html">Dpgen generators User's Manual</A></td>
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<td class="navigation" align="right" width="33%"><A HREF="node34.html">DpgenFifo</A></td>
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<ADDRESS>
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Sophie B<small>ELLOEIL</small><br>20051116.1
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