258bd053c4
* Change: In Katana::PowerRailsPlanes::Rail::doLayout(): change the delta
computation. Extend of the pitch *minus* the half wire-width *minus* 1.
So a wire at minimal with will reach exactly the previous and next
track axis. And will not be insterted in them due to the "minus 1".
TrackFixedSegments created at this stage must be flagged as
TElemBlockageNet, so that any overlap between them is not seen as an
error by the track overlap checker.
This was a problem for the clock tree wires which partly uses
pre-fixed wires, but the driver of the H-Tree is a normal signal that
must abide the usual checking.
* Change: In Katana::TrackFixedSegment::getNet(), no longer rely on the
kind of net to choose to return the actual net or the blockage one,
but uses the TElemUseBlockageNet flag.
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| CMakeLists.txt | ||
| __init__.py | ||