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riscv
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coriolis
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https://gitlab.lip6.fr/vlsi-eda/coriolis.git
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1da71ae740
coriolis
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crlcore
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symbolic
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Jean-Paul Chaput
d7931391c0
Adjusted routing pitch for METAL4 to METAL7 for FreePDK45 symbolic.
2019-09-19 23:52:03 +02:00
..
cmos
Added core2chip support for Phenitec80.
2019-09-17 17:05:54 +02:00
cmos45
Adjusted routing pitch for METAL4 to METAL7 for FreePDK45 symbolic.
2019-09-19 23:52:03 +02:00
ispd05
ISPD05 loading speed issues. IO PAD support for LEF importation.
2019-04-22 12:16:16 +02:00
phenitec06
Added core2chip support for Phenitec80.
2019-09-17 17:05:54 +02:00
vsc200
Corrections in the Dijkstra global routing (ripup) mechanism.
2018-04-16 12:10:48 +02:00