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<H1><A NAME="SECTION000340000000000000000">
DpgenFifo</A>
</H1>
<UL>
<LI><SPAN CLASS="textbf">Name</SPAN> : DpgenFifo - Fifo Macro-Generator
</LI>
<LI><SPAN CLASS="textbf">Synopsys</SPAN> :
<PRE>
Generate ( 'DpgenFifo', modelname
, param = { 'nbit' : n
, 'nword' : regNumber
, 'physical' : True
}
)
</PRE>
</LI>
<LI><SPAN CLASS="textbf">Description</SPAN> : Generates a FIFO of <code>regNumber</code> words of <code>n</code> bits named <code>modelname</code>.
</LI>
<LI><SPAN CLASS="textbf">Terminal Names</SPAN> :
<UL>
<LI><SPAN CLASS="textbf">ck</SPAN> : clock signal (input, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">reset</SPAN> : reset signal (input, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">r</SPAN> : read requested (input, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">w</SPAN> : write requested (input, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">rok</SPAN> : read acknowledge (output, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">wok</SPAN> : write acknowledge (output, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">sel</SPAN> : select the write bus (input, 1 bit)
</LI>
<LI><SPAN CLASS="textbf">datain0</SPAN> : first write bus (input, <code>n</code> bits)
</LI>
<LI><SPAN CLASS="textbf">datain1</SPAN> : second write bus (input, <code>n</code> bits)
</LI>
<LI><SPAN CLASS="textbf">dataout</SPAN> : read bus (output, <code>n</code> bits)
</LI>
<LI><SPAN CLASS="textbf">vdd</SPAN> : power
</LI>
<LI><SPAN CLASS="textbf">vss</SPAN> : ground
</LI>
</UL>
</LI>
<LI><SPAN CLASS="textbf">Parameters</SPAN> : Parameters are given in the map <code>param</code>.
<UL>
<LI><SPAN CLASS="textbf">nbit</SPAN> (mandatory) : Defines the size of the words (even, between 2 and 64)
</LI>
<LI><SPAN CLASS="textbf">nword</SPAN> (mandatory) : Defines the number of words (even, between 4 and 32)
</LI>
<LI><SPAN CLASS="textbf">physical</SPAN> (optional, default value : False) : In order to generate a layout
</LI>
</UL>
</LI>
<LI><SPAN CLASS="textbf">How it works</SPAN> :
<UL>
<LI>datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal.
</LI>
<LI>sel : when set to <code>zero</code> the datain0 is used to write the register word, otherwise it will be datain1.
</LI>
<LI>r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty).
</LI>
<LI>w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full).
</LI>
</UL>
</LI>
<LI><SPAN CLASS="textbf">Example</SPAN> :
<PRE>
from stratus import *
class inst_fifo ( Model ) :
def Interface ( self ) :
self.ck = SignalIn ( "ck", 1 )
self.reset = SignalIn ( "reset", 1 )
self.r = SignalIn ( "r", 1 )
self.w = SignalIn ( "w", 1 )
self.rok = SignalInOut ( "rok", 1 )
self.wok = SignalInOut ( "wok", 1 )
self.sel = SignalIn ( "sel", 1 )
self.datain0 = SignalIn ( "datain0", 4 )
self.datain1 = SignalIn ( "datain1", 4 )
self.dataout = SignalOut ( "dataout", 4 )
self.vdd = VddIn ( "vdd" )
self.vss = VssIn ( "vss" )
def Netlist ( self ) :
Generate ( 'DpgenFifo', 'fifo_4_16'
, param = { 'nbit' : 4
, 'nword' : 16
, 'physical' : True
}
)
self.I = Inst ( 'fifo_4_16', 'inst'
, map = { 'ck' : self.ck
, 'reset' : self.reset
, 'r' : self.r
, 'w' : self.w
, 'rok' : self.rok
, 'wok' : self.wok
, 'sel' : self.sel
, 'datain0' : self.datain0
, 'datain1' : self.datain1
, 'dataout' : self.dataout
, 'vdd' : self.vdd
, 'vss' : self.vss
}
)
def Layout ( self ) :
Place ( self.I, NOSYM, Ref(0, 0) )
</PRE>
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<ADDRESS>
Sophie B<small>ELLOEIL</small><br>20051116.1
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