Jean-Paul Chaput ec96161f0f New CRL::SubNetNames class to parse/generate VHDL vectorised subnames. ... * New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized or not and allow to generated sub-net names from it, with respect to the original vector name. Examples: * machin -> machin_hfns_0, machin_hfns_1, ... * bidule(3) -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ... Makes use of the POSIX regex library to avoid Boost dependencies.		2021-03-23 17:11:56 +01:00
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cmake_modules	Compliance with Debian 10 Buster.	2020-03-19 18:18:35 +01:00
doc	Documentation cleanup & rebuild.	2020-11-12 14:22:31 +01:00
etc	In LibreSOCIO, allow to choose between complete/abstract layout.	2020-12-07 16:41:09 +01:00
python	Fix I/O Pad ring 45 degree corners where off the foundry grid.	2020-12-09 00:05:52 +01:00
src	New CRL::SubNetNames class to parse/generate VHDL vectorised subnames.	2021-03-23 17:11:56 +01:00
CMakeLists.txt	Groudwork for routing density driven placement. Compliance with clang 5.0.1.	2019-12-09 01:57:44 +01:00