coriolis/cumulus
Jean-Paul Chaput 8f69fa668d More trials on SystemVerilog to Verilog translators.
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
    for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
    that is delegated to Surelog and just load the resulting UHDM.
      Merge with yosysnp and automatically detect if we can load the
    Python plugin or go through a script.
2023-09-19 16:01:00 +02:00
..
src More trials on SystemVerilog to Verilog translators. 2023-09-19 16:01:00 +02:00
CMakeLists.txt Remove non-needed Python Development.Module requirement in CMakeLists.txt. 2023-08-09 10:11:54 +02:00