1adefabb2f
* Bug: In CRL Core, in Vst driver, remove VhdlEntity (from Cell) and
BitProperty/Bit (from Net) with the property remove and not the
destroy() method. The BitProperty removal was completly forgotten
leading to the use of removed Signals when doing multiple saves
(hence core-dump).
* Change: In CRL Core, in Vst driver, never save as Signals the DeepNets
as they are created by a virtual flatten and do not connect any
instances at top level. Note that they will exists in the physical
file if routing layout has been created.
|
||
|---|---|---|
| .. | ||
| LibraryManager | ||
| ccore | ||
| cyclop | ||
| fonts | ||
| pyCRL | ||
| x2y | ||
| CMakeLists.txt | ||